Abstract: An offset voltage calibration method is disclosed, which is utilized for calibrating an offset voltage of an electronic device during a calibration period. The offset voltage calibration method includes generating a control signal according to an output signal of the electronic device, counting a count value and generating an offset indication signal according to the control signal, stopping counting and generating a final count value according to a compensation value after the output signal changes state, generating a calibration signal according to the count value or the final count value, and calibrating the offset voltage according to the offset indication signal and the calibration signal.

Abstract: Techniques for biasing an amplifier using a replica circuit are disclosed. In an embodiment, a replica circuit having substantially the same topology and sizing as a push-pull amplifier circuit is coupled to a main push-pull amplifier circuit. A transistor in the replica circuit may be biased using feedback to generate a predetermined DC output voltage level, and such bias level may be applied to a corresponding transistor in the main push-pull amplifier circuit. In another embodiment, a transistor in a current bias module may be used to bias corresponding transistors in the main push-pull amplifier circuit and the replica circuit. Further techniques are disclosed for configuring the amplifier to have a non-uniform step size with finer resolution at lower power levels and coarser resolution at higher power levels to reduce power consumption at lower power levels.

Abstract: The invention discloses a bias balancing circuit. The bias balancing circuit is used for balancing an output voltage outputted by an amplifier module. The amplifier module has a variable gain. The bias balancing circuit comprises a comparator and a voltage selector. The comparator is used for comparing the output voltage and a reference voltage, to generate a comparison signal. The voltage selector is used for generating a selected voltage according to the comparison signal. When the variable gain is changed to result in an offset from the output voltage to the reference voltage, the bias balancing circuit is capable of balancing the output voltage toward the reference voltage by the selected voltage.

Abstract: Variable attenuation systems having continuous input steering may be used to implement vector or quadrature modulators and vector multipliers. Discrete implementations of attenuators with continuous input steering may have two outputs which may be cross-connected to provide four-quadrant operation. A symmetrically driven center tap may provide improved zero-point accuracy.

Abstract: A hybrid broadband power amplifier module design is disclosed. In a power amplifier design, low impedance transmission lines are typically needed at the input and output of the transistor to match for its optimum source and load impedance. The peripheral of the GaN (Gallium Nitride) transistor is very small due to the high power density of the GaN transistor. The transmission line, for example a microstrip line, needs to be very wide to achieve low impedance on ceramic substrates such as Alumina. The dimensional mismatch from the low impedance transmission line to the transistor causes additional parasitic effect to the matching networks and limits the bandwidth of the amplifier. Capacitor materials are typically very high in dielectric constant; hence a single layer capacitor with small dimensions equalizes to a low impedance transmission line. Selected capacitors with proper dimensions can be used as the low impedance transmission lines in the matching networks.

Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.

Abstract: A conversion circuit is provided for a 1.5-bit ?-? class-D amplifier to improve the feedback linearity of the class-D amplifier, by periodically inverting and mixing a first positive feedback signal and a first negative feedback signal from the power stage of the class-D amplifier to generate a second positive feedback signal and a second negative feedback signal with better linearity for feedback control in the class-D amplifier.

Abstract: An amplifier stage for generating an amplified output signal from an input signal, a mobile device comprising an audio amplifier, and an amplification method for generating an amplified output signal from an input signal using an amplifier stage are described.

Abstract: A first stage electronic system for receiving charge or current from voltage-controlled sensors or detectors that includes a low input impedance current receiver/converter device (for example, a transimpedance amplifier), which is directly coupled to the sensor output, a source of bias voltage, and the device's power supply (or supplies), which use the biased voltage point as a baseline.

Abstract: Provided is a high frequency amplifier including two amplifying elements of different element sizes connected in parallel and switching the amplifying elements in accordance with a level of output power. In particular, the high frequency amplifier includes an output matching circuit for matching to characteristic impedance (50 ohms) both when the output power is high and low, and increasing impedance when the turned-off amplifying element is viewed from a connection node on an output side of the two amplifying elements. Consequently, characteristics such as high output power and high efficiency can be achieved and it is possible to prevent an amplified high frequency signal from passing around to a matching circuit on a turned-off amplifying element side.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: Techniques for integrating a common-source and common-gate amplifier topology in a single amplifier design. In one aspect, an input voltage is provided to both a common-source amplifier and a common-gate amplifier. The output voltages of the common-source amplifier and the common-gate amplifier are provided to a difference block for generating a single-ended voltage proportional to the difference between the output voltages. When applied to the design of, e.g., low-noise amplifiers (LNA's), the disclosed techniques may offer improved noise performance over the prior art.

Abstract: The present invention relates to balanced power amplifier network in combination with outphasing techniques such as Chireix. The object of the present invention is to provide a solution to the problem to combine balanced amplifiers like the current mode class D (CMCD) or class E/F with a LINC network. The main problem is that some power amplifiers have balanced output and the LINC network is single-ended so that a high power low loss transformer that works at several impedance levels is needed, which is hard to realize at cellular frequencies.

Abstract: An amplifier circuit with favorable linearity is provided. An amplifier of the present invention is provided with an amplifier MOS transistor, a diode-connected transistor block for negative feedback source impedance constituted by series-parallel connection of the limited number (including 0) of the diode-connected MOS transistors and connected to a source side of the amplifier MOS transistor, and a diode-connected transistor block for load constituted by series-parallel connection of the limited number of the diode-connected MOS transistors and connected to a drain side of the amplifier MOS transistor. A voltage gain is configured to be determined by a ratio of the sum of source impedance of the amplifier MOS transistor and the impedance of the diode-connected transistor block for negative feedback source impedance to the impedance of the diode-connected transistor block for load.

Abstract: In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation.

Abstract: An integrated HF-amplifier has an input bond pad, cells displaced in a first direction, and an output bond pad. Each has a amplifier with input pad, active area, and output pad. The active area is arranged in-between the input and output pads, and the input pad, active area, and output pad are respectively displaced in a second direction substantially perpendicular to the first direction. A first network interconnects input pads of adjacent cells, and extends in the first direction. A second network interconnects output pads of adjacent cells, and extends in the first direction. The first and second networks obtain an output signal at the output bond pad having for all interconnected cells an equal phase shift and amplitude for a same input signal at the input bond pad. At particular bias and phase shift conditions this provides a Doherty amplifier with improved efficiency at power back off.

Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

Abstract: A differential gain stage includes a plurality of programmable passive circuit component arrays operable to set a gain of the gain stage. The gain stage also includes an active switch gate control circuit and a passive switch gate control circuit. The active switch gate control circuit controls a gate voltage applied to transistor switch components of each programmable passive circuit component array as a function of the level of common mode disturbance input to the differential gain stage for common mode frequencies below a particular frequency threshold. The passive switch gate control circuit controls the gate voltage applied to the transistor switch components as a function of the level of common mode disturbance for common mode frequencies above the frequency threshold. The differential gain stage can for part of a receiver such as an xDSL receiver.

Abstract: A semiconductor integrated circuit device includes: an amplifier circuit which respectively has one or more input terminals and one or more output terminals; a replica circuit which has the same DC characteristics as those of the amplifier circuit; a reference voltage generation circuit which is connected to a bias terminal of the replica circuit, and which generates a predetermined reference voltage at the bias terminal; and a feedback circuit which takes a difference between the reference voltage generated at the bias terminal of the replica circuit and the voltage generated at a bias terminal of the amplifier circuit, and which performs feedback control by providing negative feedback of the difference to the bias terminal of the amplifier circuit so that the voltage generated at the bias terminal of the amplifier circuit is made equal to the reference voltage generated at the bias terminal of the replica circuit.

Abstract: A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.