Abstract: A memory including an input register, an input pointer circuit, and an output pointer circuit. The input register is configured to receive and latch-in valid and invalid data via an input pointer and to output the valid data via an output pointer. The input pointer circuit is configured to provide the input pointer based on a continuously running write data strobe clock signal. The output pointer circuit is configured to provide the output pointer based on an external clock signal and to update the output pointer to point to the valid data in the input register based on a write signal.

Abstract: A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.

Abstract: During iSCSI communication, according to the contents of commands issued by a host computer, the command response time is increased due to the influence of the TCP Delayed ACK. Thus, a command issued by the host computer is analyzed, the number of TCP/IP packets required for transmitting the data requested by this command is calculated, and a precedence packet is transmitted, so that no influence is experienced due to the Delayed ACK.

Abstract: A programmable-controller remote terminal apparatus of the invention shortens a system down time generated in replacing an I/O unit, in the I/O unit having a three-divided configuration of a remote terminal apparatus in which miniaturization and low-profile are developed. A programmable-controller remote terminal apparatus, which is connected to a programmable controller through a fieldbus, includes a communication unit and at least one I/O unit which can communicate with the communication unit through a serial bus line, wherein the communication unit has a device which obtains unit information for identifying each connected I/O unit and setting value information set in each I/O unit, and the communication unit has a backup device which can store the obtained unit information and setting value information of each I/O unit in a storage medium included in the communication unit.

Abstract: A data transfer control device for data transfer through a bus including a state execution circuit conducting each state process of first-Nth states in order to perform a state control of the data transfer control device, a transfer controller performing a control for the data transfer based on a result of the state process execution in the state execution circuit, a command register in which a state transition execution command is set, and a control circuit decoding the state transition execution command set in the command register and controlling the state execution circuit based on a result of the decoding, the control circuit controlling the state execution circuit to execute a Kth (1?K?N) state process if an individual state transition execution command that changes the state of the data transfer control device to the Kth state is set in the command register, and the control circuit controlling the state execution circuit to execute a plurality of state processes consecutively from a Lth (1?L?N) state to

Abstract: Methods for selectively activating one of multiple functions provided by a mobile phone are provided. An embodiment of a method for selectively activating one of multiple functions comprises the following steps. The coupling of the mobile phone to a computer system is detected. A first interface is displayed to facilitate selection of a first function from the functions. The selection of the first function is detected by the first interface. At least one software module is configured to activate the first function, thereby the computer system is directed to employ the mobile phone as a first external electronic device corresponding to the first function.

Abstract: Optimization of a use of memory buffers of a device connected to a physical link including virtual channels (VCs) while sustaining bandwidth for communication between the device and another entity, by determining an initial allocation of memory buffers of each VC. Further, the optimization is accomplished by determining whether a next VC is active or inactive. If the VC is determined to be inactive, a number of memory buffers initially allocated to the inactive channel is determined, and the memory buffers are re-allocated between the active VCs.

Abstract: A method, apparatus, and computer instructions for controlling data flow. A control message is formed for the data flow in response to an event while the data flow is occurring. The control message includes a data type, an action, and a duration. The control message is sent to a receiver data processing system, wherein the receiver data processing system modifies the data flow to the data processing system using the control message.

Abstract: An apparatus for executing user commands in digital equipment operating in a USB mass storage (UMS) mode is configured in such a manner that a USB connecting unit transmits and receives commands and data to and from a PC serving as a host through a universal serial bus (USB) port. A USB control unit controls the USB connecting unit. A storage unit stores an access command table including access commands allocated respectively to address shift values, by which addresses contained in one or more user commands received from the PC deviate from a valid address range. A microcomputer determines whether the command received through the USB connecting unit is a user command. If it is determined that the received command is a user command, the microcomputer controls executing the access commands allocated respectively to the address shift values based on the access command table.

Abstract: A communication apparatus for an electronic system is provided in accordance with the presently disclosed techniques. Specifically, in one embodiment, the apparatus includes a display base. The display base includes a body having a bay configured to receive a first electronic device and a recessed portion configured to receive a second electronic device. The display base also includes one or more cable routing features disposed within the body. One of the cable routing features is configured to route a cable connected to the first or second electronic device through a portion of the base. A system and a method for facilitating communication via a display base are also disclosed.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data transfer corresponding to the data transfer requests. The transfer controller includes a data transfer program register and active source and destination registers. The transfer controller operates from the active source and destination registers. Upon completion of a data transfer the transfer controller writes data transfer parameters from the data transfer program register to the active source and destination registers.

Abstract: The computer system is composed of an old storage apparatus, a new storage apparatus, management computer, data network and management network. Management computer gathers logs at the old storage apparatus. When data is moved from the old storage to the new storage, destination volume in the new storage apparatus is allocated and concatenated using the gathered log information and a mapping table. The system and apparatus simplifies migration processes from ordinary storage apparatus to the new storage device, which may include HDDs and FLASH memory units. The system takes into account the differences in performance characteristics of HDDs and FLASH memories, achieving improver performance of the overall storage system.

Abstract: The arrival of a new media volume or newly attached device is detected. The media or device is scanned in order to determine the type, and a complete list of installed software programs registered to handle the media type or device is presented to the user. This list may be generated and displayed while the disk is still being scanned. The user selects a handler for the media type or device, and may also decide if the handler will be the default handler when media type or device is subsequently encountered. The user may check and update the stored user settings to view or edit the default handlers for any media type or device. Additionally, the user is prompted to confirm or change the default handler after another registered handler of that media type has recently been installed on the machine.

Abstract: The present invention relates to a method and system for managing I/O interfaces with an array of multicore processor resources in a semiconductor chip. The I/O interfaces are connected to the processor resources through an I/O shim. An I/O interface sends a dataframe to the I/O shim. The I/O interface packetizes data to form the dataframe, based on an I/O protocol. The dataframe includes a header and the data. The I/O shim identifies a command corresponding to the dataframe by using one or more of the processor resources. The command includes a set of tasks. Subsequently, the set of tasks is executed on the data.

Abstract: Enclosure numbering is performed in redundant array of independent disk (RAID) data storage systems. If first, second, and third boards in an enclosure indicate a first enclosure number, the enclosure is indicated as having the first enclosure number. If at least the first and second boards indicate the first enclosure number, the enclosure is indicated as having the first enclosure number. If the first board does not indicate any enclosure number, indicating that the enclosure's enclosure number is unknown.

Abstract: Methods, systems, and articles of manufacture for transferring control commands to a memory device. In one embodiment, the memory device comprises at least one serial command terminal with a downstream serial command decoder for receiving and decoding external command code as a serial bit sequence. Embodiments of the invention also disclose a memory controller comprising both a multiplicity of parallel command outputs and at least one serial command output for transmitting command code to the memory device as a serial bit sequence.

Abstract: A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

Abstract: The Distributed Virtual I/O Tool replaces dedicated VIO server LPARs by distributing the virtual I/O functions across several application LPARs connected by a high-speed communication channel. The physical I/O devices are distributed across available LPARs. The Distributed Virtual I/O Tool assigns each I/O request to an appropriate I/O device. The Distributed Virtual I/O Tool monitors each I/O request and reassigns I/O devices when performance drops on a specific device or when a device is no longer available.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

Abstract: An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.