Abstract: An interface for coupling data between a host computer/server and a bank of disk drives. The interface includes a chassis having disposed therein: a pair of storage processors adapted for coupling to the host computer/server; and, a pair of management controllers in communication one with the other through a communication link. The management controllers monitor elements of the interface including fans and power supplies and control such elements in response to massages passing between the management controllers.

Abstract: Enabling user space middleware or applications to pass file name based storage requests directly to a physical I/O Adapter without run-time involvement from the local Operating System (OS)is provided. A mechanism is provided for using a file protection table (FPT) data structure, which may include a file name protection table (FNPT) and file extension protection table (FEPT), to control user space and out of user space Input/Output (I/O) operations. The FNPT has an entry for each file managed by the OS? file system and points to a segment of the FEPT. Each entry in the FEPT may include a protection domain, along with other protection table context information, against which I/O requests may be checked to determine if an application instance that submitted the I/O requests may access the file identified in the I/O requests.

Abstract: Techniques are described herein for expanding the range of data targeted in I/O requests made by clients, so that the expanded range results in aligned I/O operations within the file system. Data that is included in the expanded range, but was not actually requested by the client, is trimmed off the data chunk returned by the file system, so that the client receives only the data required by the client. The blocks that contain the partially-read data are cached, so that they can be provided to the clients in response to subsequent I/O requests, without having to retrieve the blocks again from the file system. The I/O requests of multiple clients are handled by a read scheduler that uses a single global queue for all such requests. When appropriate, the read scheduler creates companionship relationships between the requests, and services the “companion” requests based on the data returned for the requests with which the companion requests are associated.

Abstract: A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further includes respective dedicated serial data and control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller. In other embodiments, dedicated data busses are provided to an external control buffer and dedicated control busses are provided to a control buffer in the module.

Abstract: Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval (“T”), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

Abstract: A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

Abstract: The subject invention relates to systems and methods that automatically monitor computer platform components and initiate automated resource recovery procedures based on detected periods of component inactivity. In one aspect, an automated maintenance system for computer resources is provided. The system includes a controller that monitors installation and removal of system components that cooperate to facilitate various operations of a computer. A threshold component supplies time out or decay values for the devices to determine inactive periods of the devices, whereby the controller removes persistent memory references for the devices based in part on the time out values. Supervisory threshold functions can be provided to cause the system to perform maintenance operations at other desired intervals in order to allow periods of device inactivity while maintaining desired component information on the respective system.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for migrating data pages subject to DMA access by temporarily disabling selected DMA operations within a physical I/O adapter. A determination is made as to whether to disable data access DMA capabilities of the physical I/O adapter. An operating mode of the physical I/O adapter is set to a particular mode utilizing a mode bit according to the determination of whether to disable data access DMA capabilities. Only data access DMA capabilities of the physical I/O adapter are disabled when the mode bit is set. Administrative services operations continue to be performed by the physical I/O adapter when the data access DMA capabilities of the physical I/O adapter are disabled.

Abstract: A multi-functional peripheral combination apparatus includes a multi-functional peripheral, a portable electronic equipment and a transforming unit being electrically connected between the multi-functional peripheral and the portable electronic equipment for image management, file management and other administrative affairs. Furthermore, the operation applied to both of the portable electronic equipment and the multi-functional peripheral is configured to preview the working image before the processing of the multi-functional peripheral, and then to edit and revise the image.

Abstract: A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfacing to a second bursting channel, the second width not being a multiple of the first width and the first width not being a multiple of the second width. Data width conversion is performed between the first FIFO unit and the second FIFO unit to convert data moving from the first FIFO unit to the second FIFO unit from the first width to the second width, and to convert data moving from the second FIFO unit to the first FIFO unit from the second width to the first width. The sub-system also includes an Error Correcting Code interface between the first FIFO unit and the second FIFO unit for performing in-line correction.

Abstract: Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a stream of data in response to a clock signal in a first clock domain. A second circuit coupled to the first circuit receives the stream of data from the first circuit in response to a low level of an empty signal in the second clock domain. A comparator circuit coupled to receives the stream of data and the output of the second circuit. Specific applications to dual port RAMs as well as implementations in a programmable logic devices are disclosed. Various methods of testing an asynchronous data transfer are also disclosed.

Abstract: The present invention provides an information processing device that comprises an information storage section for storing device setting information of the information processing device and a program for bringing the information processing device into operation; a firmware version judgment section for comparing, upon reception of updating data that includes device setting information and version information, the version information of a program contained in the updating data and version information of the program stored in the storage section; wherein: an upgrading judgment section brings the acquirement section into operation to obtain a program corresponding to the version information of a program contained in the updating data so as to update the program stored in the storage section and the device setting information when the version information of a program contained in the updating data and the version information of the program stored in the storage section are not identical, and updates the device set

Abstract: A computerized system is described (i) which includes an interface connected with a peripheral device and (ii) which is incapable of dynamically extending bus cycle timing if required by the peripheral device to carry out a particular current operation. This computerized system includes a given peripheral device which, during normal operation of the device, can require an extension of bus cycle timing to carry out the current operation. This device generates a specific signal when the extension is required. The device is connected with the interface of the computerized system and the system is configured to cause the system (i) to recognize the specific signal and (ii) to instruct the peripheral device to retry the current operation responsive to the specific signal. In a particular embodiment, the peripheral device is a disk drive having an ATA interface and the specific signal generated by the disk drive is an IORDY signal.

Abstract: A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.

Abstract: Embodiments of the present invention provide a method and a system for monitoring a storage device for usage and warranty. In one embodiment, a data storage apparatus comprises a nonvolatile storage; and a data storage controller configured to store a log of status parameters of the data storage apparatus in the nonvolatile storage. The log of status parameters of the data storage apparatus in the nonvolatile storage is not resettable. Storing of the log of status parameters of the data storage apparatus in the nonvolatile storage cannot be disabled.

Abstract: Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs.

Abstract: A new audio playback architecture may be used, which allows the use of much larger buffering than that used by a typical audio subsystem in a computing system to improve power efficiency of the system and at the same time allows to maintain the quality (e.g., fidelity and responsiveness) of the audio playback. The audio controller in the new architecture may be made to report back to the host system a more accurate indication of which audio frame is being set to the audio codec than a currently available audio controller does. Additionally, the controller is capable of re-fetching previously buffered (but not yet transmitted) data. Furthermore, the controller may dynamically adjust the size of its local buffer.

Abstract: In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.

Abstract: One embodiment of the present invention provides a universal storage bus adaptor that can interface a host computer's bus to any of multiple types of storage devices. The universal serial bus adaptor provides transport layer functionality in such a way that a separate transport layer does not have to be provided for each type of storage device. Another embodiment of the present invention includes a file management system (or storage stack) that has a read/write chimney configured to enable a READ/WRITE operation to bypass the exception processing and management functionalities of the file management system. Bypassing these functionalities increases the processing efficiency of READ/WRITE operations.

Abstract: The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit (input-output means) and processes the data outputted from the storing unit with a control unit (processing means). The storage control unit inputs and outputs image data to and from the storing unit by the DMA method through a path via a DMA control unit and inputs and outputs other data such as a control instruction to and from the storing unit by the PIO method through a path via a PIO control unit. Image data to be inputted and outputted to and from the storing unit by the DMA method is encrypted in an input operation and decrypted in an output operation by an encryption/decryption unit provided on the input-output path for DMA method.