Abstract: An information processing apparatus communicable with a peripheral device and a terminal is provided. The information processing apparatus receives information about the peripheral device from the peripheral device and saves the information, counts the sharing rate of each peripheral device by counting, for each peripheral device, message information transmitted/received between the terminal and the peripheral device, receives, from the terminal, a request message to request the information about the peripheral device, and transmits, to the terminal, information about a peripheral device selected in accordance with a sharing rate of each peripheral device when the request message is received.

Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A storage apparatus is configured to detect a connection from a new host system having no logical unit assigned thereto. The storage apparatus assigns, if any new host system is detected, a new logical unit to that new host system. By so doing, it is possible to generate a logical unit and associate it with a relevant host system whenever a storage apparatus is introduced or a new host system is added, without input from a storage apparatus administrator at a management console. It is thus possible to simplify the storage apparatus settings required whenever a storage apparatus is introduced or a new host system is added.

Abstract: A computer program product for managing connections comprises a computer readable storage medium having the following computer instructions. The instructions cause a controller to perform: outputting an image including icons representing respective devices connected to an IEEE 1394 serial bus to display means; and establishing a logical connection between two of the connected devices by updating the contents of iPCR and oPCR stored in register spaces in the two connected devices and updating data for management of a band and a channel that is stored in a register space provided in an isochronous resource manager, which is a node for isochronous resource management on the IEEE 1394 serial bus, when a user enters a selection of the two connected devices to be logically connected to each other from among the connected devices on the bus.

Abstract: Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then manages data counters and location pointers based on the number of consecutive ones and the number of consecutive zeroes. For writes and non-cached reads, the number of zeroes is used to adjust a logical sector address without actually moving data. For cached reads, the number of zeroes is used to adjust the logical sector address and a host address pointer. The DMA context list manager also determines an instruction length based on a number of consecutive ones and issues one or more instructions for each group of consecutive ones and subtracts the instruction lengths from the overall transfer length until the transfer is complete.

Abstract: Methods and apparatus for redundancy in machine or process control systems provide redundant communication adapters located with the groups of I/O modules, so that if the first communication adapter faults or becomes unavailable, a second communication adapter will perform all of the necessary functions of the first adapter. The adapters are connected to a multiplexing module for communicating input data from the I/O modules to the communication adapters, for exchanging initialization data with the first communication adapter and the second communication adapter to initialize the redundant mode of operation and for monitoring communication of the first communication adapter and the second communication adapter on the network to start up the second adapter as the primary adapter for communicating both input data and output data with the I/O modules.

Abstract: A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer.

Abstract: Techniques for reducing dismount time for a peripheral device connected to an external host device are presented. Instead of waiting for a dismount procedure to complete, a reply message indicating that dismount operations have been completed is sent to the external host device. This triggers a message from the external host device that the peripheral device is ready to be safely removed. The peripheral device completes the dismount operations including cache and memory cleanup after the reply message indicating that dismount operations have been completed is sent to the external host device. The dismount operations may be completed under battery power if necessary. This enables quicker unplugging of the peripheral device from the external host device and can allow the peripheral device to transition from a first mode into a second mode faster.

Abstract: The invention provides a system and a method of processing keystrokes being entered in an electronic device. The method comprises: monitoring for activation of two or more keys on the device; determining whether a keystroke conflict occurs from the activation of the keys; and if a conflict has occurred, then executing further steps. The further steps include: identifying a selected key from the activated keys; generating a character associated with the selected key; and ignoring activation of any keys other than the selected key. The system comprises an electronic device with a display, a keypad and modules which perform the steps of the method as noted.

Abstract: A home gateway 30, input devices, output devices and a client are connected via a network LAN. Installed into the home gateway 30 is a server-side program 100 for performing control of input devices and output devices, edit of image, and provision of an interface window to the client 10. Once the user specifies the devices to be used for input-output of image through the client 10, the server-side program 100, according to this specification, imports the image from the input device, transfers to the output device and causes the image to be output. This enables input-output of image to be achieved without installing a device driver.

Abstract: A SES API is disclosed as an interface between SES protocol code and non-SCSI storage enclosure hardware to abstract the SES protocol code from the control of the hardware. To control the hardware, SES commands are sent to the SES protocol code. The SES protocol code is responsive to the SES commands, but has no knowledge of the hardware. The SES protocol code converts the SES command to a series of function calls. When the SES API receives the function calls, it executes the corresponding functions. The SES API includes a customer-tailored interface library of functions. The library allows the end user to provide the hardware interface routines necessary for SES to control the hardware. The functions are written as templates, separate from the SES protocol code, so that end users can modify the functions to control the hardware without having to modify or understand the SES protocol code.

Abstract: Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

Abstract: A chip with IDE host and IDE slave and corresponding self-debugging function is provided. The chip simplifies IDE debugging of a chip, which comprises a front-end and a backend, by offering separate debugging modes for an IDE host and an IDE slave on the same chip. The front-end provides output data of an internal IDE slave or output data of an external IDE slave in response to a host debug enable signal. The backend is coupled to the front-end. The backend provides functions of an internal IDE host according to the output data of the internal IDE slave or the external IDE slave, or directs the output data of the internal IDE slave to an external IDE host in response to a slave debug enable signal.

Abstract: A data storage system has a circuit board module, a set of Serial ATA devices, and a set of Serial ATA cables connecting the circuit board module to the set of Serial ATA devices. The circuit board module includes a circuit board, multiple host circuits mounted to the circuit board and multiplexer circuitry mounted to the circuit board. Each host circuit is configured to perform data storage operations on the behalf of an external client. The multiplexer circuitry is configured to (i) receive control signals from the host circuits and (ii) provide communications pathways between the host circuits and the set of Serial ATA devices in response to the control signals. Such an embodiment alleviates the need for multiple versions of disk drive assemblies and their associated costs.

Abstract: Provided are a method, system, and program for transferring data between system and storage in a shared buffer. An application requests a buffer from a component. The component allocates a buffer and returns to the application a first offset in the buffer for application data and a second offset in the buffer for a first header. The application writes the application data at the first offset in the buffer; and writes the first header at the second offset in the buffer. A second header is written to a third offset in the buffer.

Abstract: Provided are a method, system, and article of manufacture for using operation codes to control a decoder's use of a buffer to generate data from an input data stream into an output data stream. An encoder generates an input data stream for a decoder comprising at least one operation code and compressed data for an output device. The at least one operation code instructs the decoder on how to use a buffer when processing the input data stream. The decoder receives the input data stream, processes the data in the input data stream to perform an operation with respect to the buffer according to the at least one operation code, and decodes the compressed data into decompressed data to send to an output data stream to the output device.

Abstract: A data transfer control device for transferring data via a bus includes a buffer controller for controlling access to a data buffer in which a command block area, a data area and status block area are prepared, and a transfer controller for controlling data transfer. The transfer controller executes, a transaction of bulk OUT transfer in a command transport to automatically send a packet including command block data written in the command block area in response to an instruction to execute automatic bulk transfer, a transaction of one of bulk OUT transfer and bulk IN transfer in a data transport to automatically execute one of sending a packet including sending data written in the data area and receiving a packet including receiving data to be written in the data area, and a transaction of bulk IN transfer in a status transport to automatically receive a packet including status block data to be written in the status block area.

Abstract: An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.

Abstract: A system and method for setting device module loading sequence. The hardware configuration of the document processing device is scanned and relevant configuration information is collected. Following collection of the relevant configuration information, document processing device system settings are then scanned. The current hardware configuration and the system settings are then input as module loading parameters. Module dependencies and module priorities are then gathered from the system settings and used to generate a module loading sequence table. The modules designated by the table are then loaded in accordance with the generated sequence. When a module loading error is detected, the error is recorded in an error log, viewable by a system administrator, and analyzed by an error handling module. The error handling module then determines whether to halt all loading progress until the error is resolved, or alternatively continues with the module loading while simultaneously generating error log data.