Abstract: A control management system for controlling electrical devices is disclosed. The control management system comprises a plurality of electrical devices, and a keyboard-video-mouse switch. Each electrical device corresponds to a transforming unit for generating a protocol command signal, and a first protocol signal transceiver for wirelessly transmitting the protocol command signal via a communication interface. The keyboard-video-mouse switch comprises a plurality of second protocol signal transceivers, a plurality of converting modules, a plurality of system controllers, and a switch unit. Each of the second protocol signal transceiver corresponds to one of the first protocol signal transceivers and is used for receiving the protocol command signal from the corresponding first protocol signal transceiver. Each converting module, coupled to one of the plurality of second protocol signal transceivers, is used for converting the protocol command signal into a driving command.

Abstract: Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a data structure, unused bits in a data structure are identified. A number of the unused bits are then selected based on the possible unpacking combinations of the data structure. The endian bit values are set to a pattern to indicate the endianness of the data structure. Data that has been packed by a transmitting module can be unpacked by a receiving module based on the detected endian bits. An algorithm may be used to determine which unused bits to select as the endian bits.

Abstract: A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.

Abstract: A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a predetermined value during the transmission of the data word. A determination unit uses the number of clock cycles of the clock signal during which the enable signal is at the predetermined value to determine the digital interface standard on which the data word transmitted during these clock cycles is based.

Abstract: A packet transmit queue control system including a first data structure, a second data structure, a packet controller, and a port transmit controller is disclosed. The first data structure can include a plurality of linked-list data structures and can store unicast type packet pointers. The second data structure can include a plurality of first-in first-out (FIFO) structures and can store multicast type packet pointers. The packet controller can receive a first sequence of unicast and/or multicast type packets. The port transmit controller can provide a second sequence of the unicast and/or multicast type packets. Further, each of the plurality of FIFO structures can correspond to an output port of the system.

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.

Abstract: A camera interface employing a direct memory access (DMA) unit to digitally perform an image transformation such as “flipping” and “rotating” an image (e.g., to correct for X-axis, Y-axis, or XY-axes mirroring). The image transforming DMA unit includes an address generator and a data selector. The address generator appropriately modifies a frame start address, a burst transfer address, a line start address, of an image frame, based on the X, Y, or XY mirrored image mode. The data selector changes the sequences of words and of pixels in a word based upon the mirrored image mode.

Abstract: We describe and claim an improved non-volatile memory storage device including an interface select switch and associated method. The device comprises a non-volatile memory, and an interface unit including a plurality of storage interfaces, the interface unit to select a storage interface from the plurality of storage interfaces responsive to a selection signal, where the non-volatile memory to exchange data with a host external to the device via the selected storage interface. In an embodiment, the selected storage interface is an ATA storage interface to convert the exchanged data in accordance with an ATA protocol when selected responsive to the selection signal. In another embodiment, the selected storage interface is a SATA storage interface to convert the exchanged data in accordance with a SATA protocol when selected responsive to the selection signal.

Abstract: An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.

Abstract: An input signal from a set of user interface devices is captured, and the input signal is converted into a packet by a console processor. The packet is transferred to a remote processor, and the remote processor generates an update command according to the packet. The update command is transferred to the console processor, and an OSD image is generated according to the update command. The OSD image is overlapped onto a video signal from the computers, and the overlapped video signal is output to the set of the user interface devices.

Abstract: Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control a device. The processor determines whether the call is intended to change a processor operating mode from the first mode to a second mode. The state of the processor is selectively changed to a second mode in which the processor executes second mode instructions loaded in a protected section of memory inaccessible to an operating system in response to determining that the call is intended to change the processor operating mode. The second mode instructions execute the device code to control the device.

Abstract: The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.

Abstract: A hot key register request is created in an extensible firmware interface application, the hot key register request has a key number and a pointer to a hot key function for the new hot key. The hot key register request is sent to a keyboard driver in the extensible firmware interface. A hot key table is created in working storage from the hot key table in the keyboard driver, and a hot key entry is inserted into the hot key table in working storage. The entry includes the key number and pointer from the hot key register request to add the new hot key as a registered hot key. A success message is sent from the keyboard driver to the extensible firmware interface application. The success message indicates the new hot key has been registered.

Abstract: Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.

Abstract: A system and method using hardware and software components enable a storage module to collect and maintain control transaction data (e.g., directives/events) when a storage device of the module is offline or in a low power configuration. The storage module contains a nonvolatile memory cache and a module controller, and also may include a separate power source, an output display and input mechanism so that when offline, the user may display and navigate among catalog information corresponding to stored content to set up deferred events related to the content. When reconnected to a general-computing host system, the host system obtains the control transaction data from the storage module, and processes the data into file-system related events and other events to perform actions to the storage device and/or to other resources coupled to the host computer system. The host system may also cache transaction control data on the storage module's cache.

Abstract: A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

Abstract: A computer system includes a communication adapter that connects a plurality of virtualized servers to one or more support system devices. The communication adapter includes a master lock register, a processing device, a queue, and a multitude of adapter access registers. Upon initialization, a virtual server asserts ownership over the communication adapter by writing its identification into the master lock register, if the register is empty. Service requests by images are transmitted to the communication adapter with an origination identification (“ID”). This ID is placed in one of the adapter access registers and the service request is placed in the queue. When a support system device responds to the service request, the response is married to the ID and broadcast back to all connected virtualized servers.

Abstract: A system and method schedules command streams for processing by a variety of consumers. A single command stream is parsed and commands included in the command stream are output to one of the variety of consumers at a time. A pre-emptive scheduling mechanism is used so that a first consumer may yield to a second consumer when the first consumer has received a sufficient amount of commands. The pre-emptive scheduling enables several of the consumers to process commands concurrently. The pre-emptive scheduling mechanism may be implemented by a device driver inserting yield commands into the command stream or by a unit parsing the command stream.

Abstract: A storage system includes a plurality of disk drives, one or more controller boards for controlling data read and write from/to the plurality of the disk drives, and a Fibre Channel switching board for controlling path switching between the controller boards and the plurality of the disk drives. The Fibre Channel switching board has a control logical circuit for adjusting a control signal system between the controller boards and the disk drives according to a connection confirmation signal indicating whether or not the control signal cable is connected to the Fibre Channel switching board.

Abstract: A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.