Patents Examined by Herve Assouman
  • Patent number: 10629786
    Abstract: A light-emitting device and a manufacturing method thereof are provided, which device yields light exhibiting an actual hue with a deviation reduced as much as possible from a designed hue value, wherein the light is a mixture of light emitted from densely-mounted light-emitting elements and excited light from a phosphor contained in a resin sealing the light-emitting elements. The light-emitting device includes a board, light-emitting elements mounted densely on the board so that light-emitting surfaces thereof face opposite to the board, and a seal resin containing a plurality of different phosphors and covering all of the light-emitting elements, wherein the phosphors are excited by light from the light-emitting elements and deposited on upper surfaces of the light-emitting elements. A space between adjacent light-emitting elements has a length of 5 ?m or more and 120% or less of a median diameter D50 of a phosphor which has the largest average particle size of the phosphors.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: April 21, 2020
    Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN WATCH CO., LTD.
    Inventors: Sadato Imai, Masahide Watanabe, Hirohiko Ishii, Koki Hirasawa
  • Patent number: 10468324
    Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 5, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Marie Denison, Luigi Colombo, Sameer Pendharkar
  • Patent number: 10347766
    Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Shuo Ho, Chia-Ming Chang, Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien
  • Patent number: 10319692
    Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Hao-Yi Tsai, Mirng-Ji Lii
  • Patent number: 10204821
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HeonJong Shin, Sungmin Kim, Byungseo Kim, Sunhom Steve Paak, Hyunjun Bae
  • Patent number: 10177226
    Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet
  • Patent number: 10162237
    Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jee Hoon Han, Soo Chul Kim, Jae Yong Shin, Jae Hyoung Youn
  • Patent number: 10164191
    Abstract: The present invention relates to a methoxyaryl surface modifier. In addition the present invention also relates to organic electronic devices comprising such methoxyaryl surface modifier.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: December 25, 2018
    Assignees: Merck Patent GmbH, InnovationLab GmbH, Technische Universitaet Braunschweig, Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V.
    Inventors: Malte Jesper, Manuel Hamburger, Janusz Schinke, Milan Alt, Klaus Muellen
  • Patent number: 10158009
    Abstract: A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: December 18, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
  • Patent number: 10134705
    Abstract: As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuko Matsubara
  • Patent number: 10121927
    Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoo Nakayama
  • Patent number: 10090461
    Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Brian S. Doyle, Niloy Mukherjee, Uday Shah, Robert S. Chau
  • Patent number: 10090190
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-Geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 10090261
    Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Florence R. Pon, Bilal Khalaf, Saeed S. Shojaie
  • Patent number: 10056424
    Abstract: A semiconductor device includes an SOI substrate formed of a first semiconductor layer having a first conductive type, an embedded oxide film, and a circuit layer; and an interlayer insulation film formed on the SOI substrate. The SOI substrate has a circuit element region and an outer circumferential region surrounding the circuit element region. The circuit layer includes a plurality of single pixel circuits arranged in an array pattern. The single pixel circuit includes a circuit element, a diode, and a conductive portion. The diode includes a first region formed on the first semiconductor layer and a first conductive member formed on the interlayer insulation film and electrically connected to the first region. The conductive portion is electrically isolated from other elements. The conductive portion includes a second region formed on the first semiconductor layer and an electrode formed on the interlayer insulation film.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 21, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroki Kasai
  • Patent number: 10050059
    Abstract: A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively disposed on the gate insulating film; a source electrode and a drain electrode that are spaced from each other on the transparent oxide film; and a light transmissive pixel electrode electrically connected to the drain electrode. The transparent oxide film includes a conductive region and a semiconductor region. The conductive region is disposed in a lower portion of the source electrode and the drain electrode and disposed in a portion that continues from the lower portion of the drain electrode, extends to part of an upper portion of the common electrode, and forms the pixel electrode. The semiconductor region is disposed in a portion corresponding to a lower layer in a region between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunori Inoue, Koji Oda, Naoki Tsumura
  • Patent number: 10043898
    Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 7, 2018
    Assignee: Transphorm Inc.
    Inventor: Rakesh K. Lal
  • Patent number: 10032793
    Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10020338
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 10, 2018
    Assignee: INTELLECTUAL VENTURES II LLC
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 9991204
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin