Patents Examined by Hiep Nguyen
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Patent number: 9575677Abstract: The various embodiments described herein include methods and/or systems for throttling power in a storage device. In one aspect, a method of operation in a storage system includes obtaining a power metric corresponding to a count of active memory commands in the storage system, where active memory commands are commands being executed by the storage system. The method further includes, in accordance with a determination that the power metric satisfies one or more power thresholds, deferring execution of one or more pending memory commands.Type: GrantFiled: December 16, 2014Date of Patent: February 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Robert W. Ellis, James M Higgins, Mark Dancho, Ryan R. Jones
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Patent number: 9557918Abstract: Aspects of the disclosure are direct towards managing data overlay in a direct access storage device (DASD) using metadata of data stored within the DASD. The DASD receives user input. The user input includes a value indicating activation of overlay tracking for a track of the DASD. The DASD updates the metadata to indicate overlay tracking activation. The DASD detects a write request from an application to overlay data on the track. In response to overlay tracking being activated for the track, the DASD determines the access method used to transmit the write request. The DASD determines an identifier for the application. The DASD determines the identifier using the protocol of the access method. The DASD records data regarding the write request within the metadata. In response to recording the data regarding the write request, the DASD overlays the track per the write request.Type: GrantFiled: May 26, 2015Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Thomas J. Gair, Jr., Miguel A. Perez, David C. Reed, Max D. Smith
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Patent number: 9552318Abstract: Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.Type: GrantFiled: June 4, 2014Date of Patent: January 24, 2017Assignee: QUALCOMM IncorporatedInventors: Hyunsuk Shin, Henry Laurel Sanchez, Hung Quoc Vuong, Amit Gil
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Patent number: 9513695Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.Type: GrantFiled: July 26, 2013Date of Patent: December 6, 2016Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy
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Patent number: 9514082Abstract: Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.Type: GrantFiled: June 4, 2014Date of Patent: December 6, 2016Assignee: QUALCOMM IncorporatedInventors: Hyunsuk Shin, Henry Laurel Sanchez, Hung Quoc Vuong, Amit Gil
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Patent number: 9507711Abstract: In a memory system having non-volatile memory and volatile memory, write data are stored in a write-coalescing buffer in the volatile memory until the write data is written to non-volatile memory. First and second level address mapping tables are stored in the volatile memory and corresponding first and second level address mapping tables are stored in the non-volatile memory, and furthermore the second level address mapping table in the volatile memory contains entries corresponding to only a subset of the entries in the second level address mapping table in the non-volatile memory. The first address-mapping table in volatile memory includes entries storing pointers to entries in the second address-mapping table in volatile memory, entries storing pointers to locations in the write-coalescing buffer, and entries storing pointers to locations in the non-volatile memory that store data.Type: GrantFiled: May 22, 2015Date of Patent: November 29, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Dharani Kotte, Akshay Mathur, Satish B. Vasudeva, Sumant K. Patro
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Patent number: 9501394Abstract: Apparatus, method and systems for managing reference data, which can prevent duplicated data loading of reference data and eliminate redundancy of I/O operations for loading of the same reference data required by different virtual machines present in the same physical node to reduce use memory and I/O through sharing virtual machine leveled memories, are provided.Type: GrantFiled: June 9, 2015Date of Patent: November 22, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kwang-Won Koh, Kang-Ho Kim, Seung-Hyub Jeon, Seung-Jo Bae
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Patent number: 9501357Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage controller receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage controller then translates the storage command for providing the data redundancy in accordance with a second data redundancy scheme.Type: GrantFiled: August 7, 2015Date of Patent: November 22, 2016Assignee: Seagate Technology LLCInventor: Radoslav Danilak
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Patent number: 9501422Abstract: Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages.Type: GrantFiled: June 11, 2014Date of Patent: November 22, 2016Assignee: VMware, Inc.Inventors: Yury Baskakov, Peng Gao, Joyce Kay Spencer
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Patent number: 9495100Abstract: A method for defragmenting volumes in a mirrored system. The method includes suspending one or more updates from being mirrored from a first set of tracks on a first server to a second set of tracks on a second server. A defragmenting process is performed on the second server. The defragmentation process stores a before and after mapping of the second set of tracks, wherein the before and after mapping includes information identifying at least one track of the second set of tracks and a corresponding first location of the respective track before the defragmenting and a second location of the respective track after the defragmenting. The method further includes, upon the defragment process completion, relocating at least one track of the first set of tracks on the first server according to the stored before and after mapping of the corresponding second set of tracks on the second server.Type: GrantFiled: June 28, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
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Patent number: 9483185Abstract: The present disclosure is directed to gradual context saving in a data storage device. An example data storage device may comprise at least a non-volatile memory and a control module. The control module may cause context data to be gradually saved to the non-volatile memory based on monitoring write activity to the nonvolatile memory, wherein the context data may correspond to a current state of the data storage device. The control module may cause context data to be saved based on a budget ratio. For example, a budget ratio may compare an amount of total budget consumed (e.g., based a capacity of the data storage device, an amount of data stored in the data storage device, a target time-to-ready for the data storage device, etc.) to an amount of total context data that has already been written to the non-volatile memory.Type: GrantFiled: December 16, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: David J. Pelster, Xin Guo, David M. Jones
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Patent number: 9483211Abstract: A storage apparatus includes a processing unit that functions a SAN OS which performs SAN control and a NAS OS which performs NAS control to be operated on a virtualized OS, an inter-OS communication unit that transmits and receives data between the NAS OS and the SAN OS, a transmission controller that transmits a NAS input/output request received in the NAS OS to the SAN OS through the inter-OS communication unit, and a NAS request processing unit that processes the NAS input/output request received from the transmission controller in the SAN OS. With this configuration, the NAS and the SAN can be efficiently integrated in a storage apparatus.Type: GrantFiled: August 29, 2014Date of Patent: November 1, 2016Assignee: FUJITSU LIMITEDInventor: Masahiko Okajima
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Patent number: 9483414Abstract: Systems and methods for virtual machine live migration. An example method may comprise: identifying, by a first computer system executing a virtual machine undergoing live migration to a second computer system, a plurality of stable memory pages comprised by an execution state of the virtual machine, wherein the plurality of stable memory pages comprises memory pages that have not been modified within a defined period of time; transmitting the plurality of stable memory pages to the second computer system; determining that an amount of memory comprised by a plurality of unstable memory pages is below a threshold value, wherein the plurality of unstable memory pages comprises memory pages that have been modified within the defined period of time; and transmitting the plurality of unstable memory pages to the second computer system.Type: GrantFiled: November 25, 2013Date of Patent: November 1, 2016Assignee: Red Hat Israel, Ltd.Inventors: Michael Tsirkin, Karen Noel
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Patent number: 9471511Abstract: The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution. The technique is based upon identifying at least one conflicting data-block having a memory mapping indication to a designated memory cache-line and preventing the conflicting data-block from being cached. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user.Type: GrantFiled: November 24, 2013Date of Patent: October 18, 2016Assignee: Truly Protect OYInventors: Michael Kiperberg, Amit Resh, Nezer Zaidenberg
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Patent number: 9471225Abstract: A method, information processing system, and computer readable storage medium, vary a maximum heap memory size for one application of a plurality of applications based on monitoring garbage collection activity levels for the plurality of applications, each application including a heap memory, and unused memory in the heap memory being reclaimed by a garbage collector.Type: GrantFiled: August 25, 2015Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Norman Bobroff, Arun Iyengar, Peter Westerink
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Patent number: 9471255Abstract: A mechanism is provided for tape writing of small transactions. A first file is written as a plurality of fixed-length data sets (DS), the DS number of the final DS in the plurality of DS is stored in memory as #N(DS#N) and the WP number as #M(WP#M), and the final first file and the second file in the DS following the final DS(DS#N, WP#M) containing the first file are packed and written in sequential DS units, and are stored as DS#N, DS#N+1, etc. and WP#M+1 in sequential order in DS containing the second file. The remaining first, second, or third file is packed and DS#N with WP#M is overwritten as DS#N with WP#M+2, and the remaining #N in the DS numbers of the second file and the third file in the subsequent DS are written as DS#N+1, N+2, etc. with WP#M+2, and the DS#N, #N+1, #N+2, etc. with WP#M+2 are stored.Type: GrantFiled: November 17, 2015Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Takamasa Hirata, Setsuko Masuda, Yuhko Mori, Yutaka Oishi, Terue Watanabe
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Patent number: 9471512Abstract: A Flash-based storage system, card, and/or module comprises a Flash controller configured to encrypt the data pages of a page stripe by shuffling the data pages, including loading each data page into a data shuffling buffer in a sequential order relative to other data pages in the page stripe, and thereafter unloading each data page in a non-sequential order relative to other data pages in the page stripe. The Flash controller is also configured to scramble the data pages of the page stripe by performing a bitwise logical operation on the data pages that are unloaded from the data shuffling buffer. A user key and one or more system keys are used to perform the shuffling and scrambling. The Flash controller is further configured to flush the user key by bypassing the system's backup power supply and performing an emergency system shutdown without backing up system data.Type: GrantFiled: November 16, 2015Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp
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Patent number: 9465548Abstract: Methods and systems for managing resources in a networked storage environment are provided. One method includes using a queuing model for a resource that processes a plurality of requests at a networked storage environment for predicting a relationship between latency and utilization of the resource. The queueing model uses inter-arrival time and service time to determine latency, where inter-arrival time is a duration that tracks when requests arrive at the resource and the service time tracks a duration for servicing the requests by the resource. The method further includes identifying optimum utilization of the resource using the predicted relationship between latency and utilization, where the optimum utilization is an indicator of resource utilization beyond which throughput gains for a workload is smaller than increase in latency; and determining available performance capacity for the resource using the optimum utilization and actual utilization of the resource.Type: GrantFiled: July 22, 2015Date of Patent: October 11, 2016Assignee: NETAPP, INC.Inventors: Curtis Hrischuk, Alma Dimnaku, Phil Larson
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Patent number: 9465757Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.Type: GrantFiled: May 30, 2014Date of Patent: October 11, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Son, Uk-song Kang, Chul-woo Park, Seong-young Seo
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Patent number: 9454327Abstract: Data storage using application storage analytics that: (i) runs a set of application(s) that use a thin provision data storage device for data storage; (ii) determines a set of runtime behavior(s) of the set of applications(s) with respect to use of the thin provisioning data storage device for data storage; and (iii) calculates a runtime representation capacity based on a predetermined over-provisioning ratio and the set of runtime behavior(s).Type: GrantFiled: August 29, 2014Date of Patent: September 27, 2016Assignee: International Business Machines CorporationInventors: Sandeep R. Patil, Riyazahamad M. Shiraguppi, Gandhi Sivakumar, Matthew B. Trevathan