Patents Examined by Hiep Nguyen
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Patent number: 9454328Abstract: Provided is a method of distributedly storing an individual content in a hierarchical storage system including a solid state storage having a plurality of solid state disks, a hard disk storage having a plurality of hard disks, and a tape storage. The method may include determining a target content to store and an inquiry frequency and a required minimum transmission rate of the target content upon receipt of a request message from a client device, classifying the target content as at least one of a low demanded content, a normal demanded content, a high demanded content, a low transmission rate content, a normal transmission rate content, and a high transmission rate content based on the inquiry frequency and the required minimum transmission rate of the target content, and distributedly storing the target content through at least one of the solid state storage, the hard disk storage, and the tape storage based on the classification result and a distribution and buffering policy.Type: GrantFiled: December 24, 2014Date of Patent: September 27, 2016Assignee: KT CORPORATIONInventors: Hyong-Muk Lim, Bom-Soo Kim, Choon-Gul Park, Ki-Tae Jeong
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Patent number: 9448930Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: GrantFiled: August 24, 2015Date of Patent: September 20, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 9436608Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.Type: GrantFiled: February 12, 2015Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ansu A. Abraham, Daniel V. Rosa, Donald W. Schmidt
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Patent number: 9436600Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.Type: GrantFiled: June 11, 2014Date of Patent: September 6, 2016Assignee: SVIC No. 28 New Technology Business Investment L.L.P.Inventor: Hyun Lee
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Patent number: 9430393Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.Type: GrantFiled: December 24, 2014Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prashant Dinkar Karandikar, Mihir Mody, Hetul Sanghavi, Vasant Easwaran, Prithvi Y. A. Shankar, Rahul Gulati, Niraj Nandan, Subrangshu Das
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Patent number: 9411814Abstract: Predicting what content items a user finds important and sending those items to a cache on the user's device at times when doing so will not drain resources and will not result in expensive data rates. Applying a ranking function that examines recency and other content metadata associated with the user's content items stored in a synchronized content management system. Determining how much of a ranked list of content items to cache and deciding when is a good time to send content items to the local cache.Type: GrantFiled: January 6, 2014Date of Patent: August 9, 2016Assignee: Dropbox, Inc.Inventors: Daniel Kluesing, Rasmus Andersson
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Patent number: 9383935Abstract: In a computer system with multiple central processing units (CPUs), initialization of a memory management unit (MMU) for a secondary CPU is performed using an exception generated by the MMU. In general, this technique leverages the exception handling features of the secondary CPU to switch the CPU from executing secondary CPU initialization code with the MMU “off” to executing secondary CPU initialization code with the MMU “on.” Advantageously, in contrast to conventional techniques for MMU initialization, this exception-based technique does not require identity mapping of the secondary CPU initialization code to ensure proper execution of the secondary CPU initialization code.Type: GrantFiled: December 16, 2014Date of Patent: July 5, 2016Assignee: VMware, Inc.Inventors: Andrei Warkentin, Harvey Tuch
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Patent number: 9378149Abstract: A method for rebuilding an in-memory data structure. The method includes selecting a table of contents (TOC) entry of a TOC page in persistent storage, where the TOC entry includes an object identifier (ID) of an object, an offset ID, and a birth time. The method further includes determining, based on the object ID, that the in-memory data structure includes object metadata for the object including a mod time and an object map pointer to an object map tree. The method further includes that the birth time in the TOC entry is greater than the mod time, updating a stored physical address in the object map tree based on the offset ID to a physical address derived from the TOC entry; and updating the mod time stored in the object metadata to the birth time.Type: GrantFiled: August 29, 2014Date of Patent: June 28, 2016Assignee: EMC CorporationInventor: Jeffrey S. Bonwick
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Patent number: 9372802Abstract: A data writing method, a hard disc module, and a data writing system for writing data into the hard disc module are provided, wherein the hard disc module includes a plurality of memory units. The data writing method includes the following steps. A cache data is received and a data class of the cache data is determined. If the data class of the cache data belongs to a first type, the cache data is distributed and written to the memory units. If the data class of the cache data belongs to a second type, the cache data is written to one of the memory units.Type: GrantFiled: June 4, 2014Date of Patent: June 21, 2016Assignee: Acer IncorporatedInventors: Po-Wei Wu, Ta-Wei Chang, Hsung-Pin Chang
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Patent number: 9367241Abstract: In one embodiment, a node of a cluster is coupled to a storage array of storage devices. The node executes a storage input/output (I/O) stack having a redundant array of independent disks (RAID) layer that organizes the storage devices within the storage array as a plurality of RAID groups. Configuration information is stored as a cluster database. The configuration information identifies the RAID groups associated with the storage devices. Each RAID group is associated with a plurality of segments and each segment has a different RAID configuration.Type: GrantFiled: September 15, 2015Date of Patent: June 14, 2016Assignee: NetApp, Inc.Inventors: Rajesh Sundaram, Bharat Baddepudi
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Patent number: 9361243Abstract: A system, apparatus, method, or computer program product of restricting file access is disclosed wherein a set of file write access commands are determined from data stored within a storage medium. The set of file write access commands are for the entire storage medium. Any matching file write access command provided to the file system for that storage medium results in an error message. Other file write access commands are, however, passed onto a device driver for the storage medium and are implemented. In this way commands such as file delete and file overwrite can be disabled for an entire storage medium.Type: GrantFiled: July 31, 2012Date of Patent: June 7, 2016Assignee: KOM Networks Inc.Inventor: Kamel Shaath
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Patent number: 9354812Abstract: Various embodiments of methods and systems for dynamically managing the capacity utilization of a memory component in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through dynamic compression and decompression within a memory subsystem. Based on parameters of the SoC that are indicative of a quality of service (“QoS”) level, a memory controller may determine that the format of the data in a write request should be converted and stored in a relinked memory address. Subsequently, a primary memory address associated with the data may be released for storage of different data. Similarly, embodiments may return data requested in a write request in a format different than that which was requested.Type: GrantFiled: February 12, 2015Date of Patent: May 31, 2016Assignee: QUALCOMM INCORPORATEDInventors: Steven Der-Chung Cheng, Vinay Mitter
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Patent number: 9355037Abstract: Methods, systems, and computer-readable storage media for providing a worklist of a user with at least one item. In some implementations, actions include determining one or more timestamps, each timestamp indicating a time, at which an item cache was synchronized for a respective provider of one or more providers, transmitting one or more requests to one or more respective providers of the one or more providers, the one or more requests each including the one or more timestamps and indicating a user, receiving one or more responses, each response including a sub-set of items, each item in the sub-set of items being included in the sub-set of items based on the one or more timestamps, populating the worklist of the user with one or more items in the sub-set of items reusing a previously synchronized worklist database cache, and providing the worklist for display to the user on a display.Type: GrantFiled: August 29, 2014Date of Patent: May 31, 2016Assignee: SAP SEInventors: Veselin Veselinov, Valeri Nikolov
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Patent number: 9348516Abstract: A storage system includes: a first storage unit; a second storage unit that has an access speed higher than an access speed of the first storage unit; and a storage controller that collects load information about respective loads in a plurality of areas in the first storage unit, selects a candidate area in the first storage unit which is to be migrated, based on the collected load information, and migrates data in the selected candidate area, to the second storage unit.Type: GrantFiled: November 25, 2013Date of Patent: May 24, 2016Assignee: FUJITSU LIMITEDInventors: Kazuichi Oe, Motoyuki Kawaba
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Patent number: 9342418Abstract: When a redundancy failures occurs in sequentiality-guaranteed data transfer, data transfer in a short period of time is resumed such that wherein when a factor by which the second storage device stops processing of the storage system is multiple failures of the two or more redundant control devices during a process of developing data to a storage medium in the second storage device, a session managing unit sets inconsistency as the copy session state, and a buffer managing unit sets the buffer data lost state, and when a data transfer process is resumed between the first storage device and the second storage device, the session managing unit sets consistency as the copy session state when the buffer data lost state is set by the buffer managing unit.Type: GrantFiled: May 30, 2014Date of Patent: May 17, 2016Assignee: FUJITSU LIMITEDInventor: Takashi Kawada
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Patent number: 9342245Abstract: Allocating a resource of a storage device to a storage optimization operation. An available resource of the storage device is monitored. Determining an allocation proportion of the resource allocated to the storage optimization operation, based on at least one of historical running information and a predicted value of a performance improvement caused by the storage optimization operation. Allocating the resource of the storage device to the storage optimization operation based on the available resource and the allocation proportion.Type: GrantFiled: August 29, 2014Date of Patent: May 17, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Xiaoyu Hu, Nikolas Ioannou, Ioannis Koltsidas, Yang Liu, Mei Mei, Paul H. Muench, Roman A. Pletka, ZhiQiang Wang
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Patent number: 9336140Abstract: Data storage management by determining, for leaf and summary storage spaces of a data storage space hierarchy having at least two leaf storage spaces descending from at least one summary storage space, an invariant leaf attribute value for each leaf attribute type, an invariant summary attribute value for each descending leaf attribute type as a sum of the invariant leaf attribute values of all leaves descending from the summary storage space, and for each leaf, a variable leaf attribute value for each leaf attribute type, and, for each summary storage space, a variable summary attribute value for each descending leaf attribute type, where for each summary storage space, and for each storage space immediately descending from the summary storage space, each variable leaf attribute value of the immediately descending storage space is expressed as a proportion of the variable summary attribute value for the same attribute type.Type: GrantFiled: December 28, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Ashraf Haib, Ateret Anaby-Tavor, Moran Gavish, Lior Limonad, Sergey Zeltyn
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Patent number: 9335941Abstract: A method, system, and computer program product comprising using a tracking structure to map a first portion and a second portion of a non-volatile storage medium to a logical representation of the non-volatile storage medium; wherein the first portion is presented by the logical representation as writable storage and using the tracking structure to enable the logical representation to present the data written to the second portion as the data corresponding to the write in the first portion.Type: GrantFiled: February 25, 2015Date of Patent: May 10, 2016Assignee: EMC CorporationInventor: Roy E Clark
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Patent number: 9330015Abstract: Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages.Type: GrantFiled: June 11, 2014Date of Patent: May 3, 2016Assignee: VMware, Inc.Inventors: Yury Baskakov, Peng Gao, Joyce Kay Spencer
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Patent number: 9330025Abstract: A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.Type: GrantFiled: July 26, 2013Date of Patent: May 3, 2016Assignee: CANON KABUSHIKI KAISHAInventor: Wataru Ochiai