Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual GUID Partition Table (GPT) disk to the block-level data volume, accessing one or more mount paths established by the virtual GPT disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual GPT disk.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request from a process to access data is a system, determine if the data is in a virtualized protected area of memory in the system, and allow access to the data if the data is in the virtualized protected area of memory and the process is a trusted process. The electronic device can also be configured to determine if new data should be protected, store the new data in the virtualized protected area of memory in the system if the new data should be protected, and store the new data in an unprotected area of memory in the system if the new data should not be protected.

Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Abstract: A virtualized storage array provides deduplication for a primary storage array that supports VVOLs. The VVOLs may be created for VMs that support host applications and guest OSs in a VDI environment. A VVOL is initially created as a virtualized managed drive that is backed by the virtualized storage array. The data is deduped by the virtualized storage array. After deduplication the data is either maintained on the virtualized storage array or moved to the primary storage array based on satisfying deduplication criteria such as reduction ratio.

Abstract: A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.

Abstract: A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory.

Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.

Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.

Abstract: An apparatus and program storage device for maintaining data is provided that includes receiving primary data at a first node, receiving mirrored data from a second and third node at the first node, and mirroring data received at the first node to a second and third node.

Abstract: A cache control system is disclosed for use with data storage apparatus having a movably mounted storage element, such as a magnetic or optical disk and solid-state cache memory, in which the storage element is not at operating speed when data access has not occurred during a predetermined time period, comprising means arranged to access data stored on the storage element if a read or write request cannot be satisfied via access to the cache memory and a cache replacement mechanism for transferring data between the cache memory and the storage element to maintain consistency of data therebetween. The system is characterized in that the cache replacement mechanism performs data transfers between the cache memory and the storage element only while the storage element is at operating speed after a read or write request has given rise to an access to the storage element.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Abstract: Secure erase of files and unallocated sectors on storage media such that any previous data is non-recoverable. The database contains sets of data patterns used to overwrite the data on different physical media. The software programs manage the overwriting process automatically when a file has been deleted. When de-allocated sectors in the file system are pruned from a file or escaped the file deletion process also finds them. Data will never be found on deleted sectors or on pruned sectors is overwritten.

Abstract: A tile for use in a tiled storage array provides re-organization of values within the tile array without requiring sophisticated global control. The tiles operate to move a requested value to a front-most storage element of the tile array according to a global systolic clock. The previous occupant of the front-most location is moved or swapped backward according to the systolic clock, and the new occupant is moved forward according to the systolic clock, according to the operation of the tiles, while providing for multiple in-flight access requests within the tile array. The placement heuristic that moves the values is determined according to the position of the tiles within the array and the behavior of the tiles. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the tile array.

Abstract: A method of managing and restoring an identifier of a storage device and an apparatus therefor are provided. The method includes the operations of generating a storage device identifier; recording the storage device identifier in a non-volatile memory of a host; generating an identifier file including the storage device identifier and a host identifier; and recording the identifier file in the storage device. By doing so, the method and apparatus can efficiently and securely manage the storage device.

Abstract: The present invention provides a disk drive storage defragmentation system, comprising providing a cache buffer system coupled to a host system, coupling a disk drive storage system to the cache buffer system, performing a defragmentation process on the disk drive storage system utilizing the cache buffer system and servicing a data access request by the host system from the cache buffer system.

Abstract: A solid state disk system is disclosed. The system comprises a user token and at least one level secure virtual storage controller, coupled to the host system. The system includes a plurality of virtual storage devices coupled to at least one secure virtual storage controller. A system and method in accordance with the present invention could be utilized in flash based storage, disk storage systems, portable storage devices, corporate storage systems, PCs, servers, wireless storage, and multimedia storage systems.

Abstract: A dummy write operation is disclosed that mimics an actual write operation to a memory array. In some implementations, a dummy write operation mimics an actual write operation by starting a charge pump, selecting a correct data line in the memory array, and by following the sequencing of an actual write operation. By mimicking an actual write operation, an attacker cannot use power analysis to distinguish between dummy and actual write operations. For example, PIN comparison operations would present the same or substantially the same power trace for both positive and negative comparisons, making it difficult for an attacker to determine if a retry count was written to NVM.

Abstract: Methods, systems, and articles for receiving, by a lock-free vector of a computing device, a request from a thread of the computing device to write data to the lock-free vector are described herein. In various embodiments, the lock-free vector may then determine whether the lock-free vector is growing and, if the lock-free vector is not growing, may allocate a first portion of memory of the lock-free vector exclusively to the requesting thread. In some embodiments, the allocating may comprise allocating using a resource allocator of the lock-free vector.

Abstract: Methods, systems and computer program products to maintain cache coherency, in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.