Abstract: Methods, systems, and computer program products are included for switching from a first guest virtual address (GVA)-to-host physical address (HPA) translation mode to a second GVA-to-HPA translation mode. A method includes comparing, by a hypervisor, a number of translation lookaside buffer (TLB) misses to a miss threshold, the hypervisor being in a first GVA-to-HPA translation mode. The method includes switching from the first GVA-to-HPA translation mode to a second GVA-to-HPA translation mode if the number of TLB misses satisfies the miss threshold.

Abstract: A storage system, a computer program product and method for replicating a storage entity to a group of storage systems. The method may include splitting the storage entity, by a given storage system, to provide storage entity portions; generating, by the given storage system, storage entity portions information for distributing the storage entity portions between all storage systems of the group so that each storage system of the group eventually receives the storage entity portions; transmitting the storage entity portions, from the given storage system, to storage systems of the group; wherein the transmitting comprises transmitting different storage entity portions from the given storage system to different storage systems of the group; sending, by the given storage system, the storage entity portions information to at least some storage systems of the group; and attempting to verify, by the given storage system, that all the storage systems of the group received all the storage entity portions.

Abstract: A storage system in one embodiment comprises a host processor that includes a first non-volatile memory. The storage system further comprises a storage device that is coupled to the host processor. A designated portion of the first non-volatile memory is bound to the storage device responsive to storage of binding information in at least one partition table associated with the first non-volatile memory. The storage device may include a storage controller that includes a configuration register space. The binding information may be copied from the one or more partition tables to the configuration register space in conjunction with a boot operation of the host processor. The host processor illustratively comprises a storage device driver having access to the binding information copied to the configuration register space of the storage device. The storage device driver may be configured to utilize the designated portion of the first non-volatile memory that is bound to the storage device as a write back cache.

Abstract: Systems and methods of the present disclosure are directed to defining a data store format for storing state information related to border-gateway protocol (BGP) routing information base (RIB) entries, BGP Neighbor Tables, intermediate system-intermediate system (IS-IS) adjacencies, Link-State Databases, Interface information, Chassis information, etc in a binary format. A brick data store (BDS) system can define tables, table properties, objects and attributes for an application in the system using configuration files expressed in Java Script Object Notation (JSON). The data format can be uniform across inter-process communication, file and in-memory representation.

Abstract: A Memory Merging Function “MMF” for merging memory pages. A hardware system comprises a set of memory blades and a set of computing pools. At least one instance of an operating system executes on the hardware system. The MMF is independent of the operating system. The MMF finds a first and a second memory page. The first and second memory pages include identical information. The first and second memory pages are associated with at least one computing unit of the computing units. The MMF obtains a respective memory blade parameter relating to memory blade of the first and second memory pages and a respective latency parameter relating to latency for accessing the first and second memory pages. The MMF releases at least one of the first and second memory pages based on the respective memory blade and latency parameters.

Abstract: A parallel processing device includes a management unit, a plurality of nodes, and a controller that controls each of the plurality of nodes in accordance with a first command transmitted from the management unit. The controller includes a command storage that stores a second command generated a previous time, a command type identification unit that identifies a command type of the first command transmitted from the management unit, and a command generator that generates a third command by using the second command according to the command type.

Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.

Abstract: A computer system includes a main memory, a lower class memory, and a secondary storage medium and executes an operating system, an in-memory computing program, and a prefetch optimizer program. The in-memory computing program writes processing target data including a plurality of data objects stored in the secondary storage medium into a plurality of continuous areas on a virtual memory space and executes a process while accessing the continuous area. When detecting that the operating system executes a class-in process triggered upon a page fault for a predetermined virtual page, the prefetch optimizer program acquires information of the continuous area from the in-memory computing program and directs the operating system to execute a class-in process for virtual pages included in the predetermined continuous area including the predetermined virtual page.

Abstract: It is possible to prevent unoccupied blocks from being depleted by a write of logical-physical management information. A processor is capable of performing an unoccupied user block generation process by moving user data stored in allocated user blocks in order to generate unoccupied user blocks serving as unoccupied blocks among allocated user blocks, and performing an unoccupied meta block generation process by moving meta data stored in allocated meta blocks in order to generate unoccupied meta blocks serving as unoccupied blocks among the allocated meta blocks. The processor calculates the number of unoccupied meta blocks to be consumed, that is, the number of unoccupied meta blocks to be consumed by the unoccupied user block generation process. The processor performs the unoccupied meta block generation process based on the number of unoccupied meta blocks to be consumed.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: A method, information processing system, and computer readable storage medium, periodically monitor, with a processing system, information related to an application's memory usage including a maximum heap memory size, an in use heap memory size, and a garbage collection activity level. Based on determining that the garbage collection activity level is below a first threshold, estimating an amount of memory that can be released from the application by reducing the maximum heap memory size. Based on determining that the estimated amount of memory that can be released from the application is above a second threshold, attempting to release memory from the application.

Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: An exemplary embodiment provides a non-transitory computer-readable storage medium with an executable information processing program stored thereon. The executable information processing program causes a computer of an information processing apparatus having a storage that stores a plurality of contents to perform designating an amount of data, selecting at least one content from among the plurality of contents based on the designated amount of data, and erasing the selected content from the storage in response to an operation by a user.

Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Abstract: A page aligning method for a data storage device is provided. The data storage device includes a non-volatile memory and the page aligning method includes steps of: executing a system initialization on the non-volatile memory to obtain a remaining storage capacity; selecting a number from a lookup table as an initial storage capacity according to the remaining storage capacity and a lookup table; and referring the initial storage capacity as a fixed capacity in the data storage device and writing the initial storage capacity into the non-volatile memory. A lookup table generating method and the data storage device are also provided.

Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.

Abstract: Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (CDir) for providing cache coherence in the multi-compute-engine systems is described. The CDir comprises a common pattern aggregated entry for one or more cache lines from amongst a plurality of cache lines of a shared memory. The one or more cache lines that correspond to the common pattern aggregated entry are associated with a common sharing pattern from amongst a predetermined number of sharing patterns that repeat most frequently in the region.

Abstract: A processing device for executing distributed memory operations using spatial processing units (SPU) connected by distributed channels is disclosed. A distributed channel may or may not be associated with memory operations, such as load operations or store operations. Distributed channel information is obtained for an algorithm to be executed by a group of spatially distributed processing elements. The group of spatially distributed processing elements can be connected to a shared memory controller. For each distributed channel in the distributed channel information, one or more of the group of spatially distributed processing elements may be associated with the distributed channel based on the algorithm. By associating the spatially distributed processing elements to a distributed channel, the functionality of the processing element can vary depending on the algorithm mapped onto the SPU.

Abstract: Facilitating recording a trace of code execution using way-locking in a set-associative processor cache. A computing device reserves cache line(s) in set(s) of cache lines of a set-associative cache for caching only locations in the system memory that are allocated to a particular executable entity. During a traced execution of the particular executable entity, the computing device detects that a cache miss has occurred on a location in the system memory that is allocated to a particular executable entity, and that a value at the location of system memory is being cached into one of the reserved cache lines. Based on the value at the location of system memory being cached into a reserved cache line, the computing device logs into a trace data stream at least a portion of the value at the location of system memory being cached into the reserved cache line.