Patents Examined by Hiep T. Nguyen
  • Patent number: 10552061
    Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Jared M. Minch, Beth A. Peterson
  • Patent number: 10540240
    Abstract: Embodiments of the present disclosure disclose a solution for data backup and recovery in a storage system. When a source device in the storage system backs up, to a backup-end device, a data block that is written after a snapshot Sn, the source device performs a logical operation such as an exclusive-NOR or exclusive-OR operation on the written data block and an original data block, which is recorded in the snapshot Sn, of the written data block, and then compresses a data block obtained after the logical operation, which improves a compression ratio of a data block, thereby reducing an amount of data that is sent to the backup-end device, and saving transmission bandwidth. The solution may be further applied to a scenario of data recovery in a storage system.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chengwei Zhang, Chuanshuai Yu, Zongquan Zhang
  • Patent number: 10535417
    Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining a margin between the CDF-based data at a particular codeword frequency and one of the thresholds.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, David Miller
  • Patent number: 10528285
    Abstract: A data storage device capable of just partially executing a read/write command issued by a host is disclosed. The data storage device uses a controller to perform a partial execution of a first read/write command issued by the host, and returns a breakpoint of the first read/write command to the host and returns information that the first read/write command is in a partial completion status to the host to drive the host to further issue a second read/write command. In this manner, fewer computational resources are required in determining read/write command granularity.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: January 7, 2020
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Zhen Zhou
  • Patent number: 10521355
    Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
  • Patent number: 10521119
    Abstract: The described technology is generally directed towards a hybrid copying garbage collector in a data storage system that processes low capacity real chunks and virtual chunks (which reference data on other storage systems) into real chunks with a relatively high data capacity utilization. Real and virtual chunks with low capacity utilization are detected and copied into a higher capacity utilization real chunk, after which the low capacity chunks are deleted and their space reclaimed. As a result, much of the virtual chunk data that is to be migrated into a real chunk in the data storage system is migrated during garbage collection instead of as a separate migration process. Only the virtual chunk data that is relatively high capacity needs to be processed into real chunks by a separate migration process.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 31, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Mark A. O'Connell
  • Patent number: 10521139
    Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 10521135
    Abstract: A data storage system includes a head node and mass storage devices. The head node is configured to flush data stored in a storage of the head node, based at least in part on one or more triggers being met, from the storage of the head node to a set of the mass storage devices of the data storage system. The flushed data is written to a segment of free storage space across the set of the mass storage devices allocated for the given data flush operation. In some embodiments, a head node may flush both current version data and point-in-time version data to the set of mass storage devices. Also, the data storage system maintains an index that indicates storage locations of data for particular portions of a volume before and after the data is flushed to the set of mass storage devices.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 31, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Norbert Paul Kusters, Nachiappan Arumugam, Andre Podnozov, Shobha Agrawal, Shreyas Ramalingam, Danny Wei, David R. Richardson, Marc John Brooker, Christopher Nathan Watson, John Luther Guthrie, II, Ravi Nankani
  • Patent number: 10509579
    Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining an intersection between the CDF-based data and one of the thresholds.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, David Miller
  • Patent number: 10509571
    Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. The first block among the blocks has a minimal erase count in the blocks. When determining that a difference between an average erase count of the blocks and the minimal erase count exceeds a cold-data threshold, the controller selects the first block to be a source block. When a data migration of a data-moving process is executed, the controller moves the data of the source block to a target block.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 17, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Zhongyi Gao, Xiaoyu Yang
  • Patent number: 10503427
    Abstract: A pod, the pod including the dataset, a set of managed objects and management operations, a set of access operations to modify or read the dataset, and a plurality of storage systems, where: management operations can modify or query managed objects equivalently through any of the storage systems, access operations to read or modify the dataset operate equivalently through any of the storage systems, each storage system stores a separate copy of the dataset as a proper subset of the datasets stored and advertised for use by the storage system, and operations to modify managed objects or the dataset performed and completed through any one storage system are reflected in subsequent management objects to query the pod or subsequent access operations to read the dataset.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 10, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Par Botes, John Colgrove, Alan Driscoll, David Grunwald, Steven Hodgson, Ronald Karr
  • Patent number: 10496549
    Abstract: A memory management method and a storage controller using the same are provided. The memory management method includes: establishing an array; selecting a first block from spare blocks at an initial time point and storing a first index number of the first block to a look-ahead block; adding the first index number in the look-ahead block to the array at a first time point, selecting a second block from the spare blocks and replacing the first index number stored to the look-ahead block with a second index number of the second block, and programming the first block; and adding the second index number in the look-ahead block to the array at a second time point, selecting a third block from the spare blocks and replacing the second index number in the look-ahead block with a third index number of the third block, and programming the second block.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 3, 2019
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Shih-Tien Liao, Yu-Hua Hsiao
  • Patent number: 10489306
    Abstract: A data processing system incorporates a cache system having a cache memory and a cache controller. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with an equal preference for eviction. The cache controller provides a further selection among this plurality of candidates based upon content data read from those candidates themselves as part of the cache access operation which resulted in the cache miss leading to the cache replacement requiring the victim selection. The content data used to steer this second stage of victim selection may include transience specifying data and, for example, in the case of a cache memory comprising a translation lookaside buffer, page size data, type of translation data, memory type data, permission data and the like.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 26, 2019
    Assignee: ARM Limited
    Inventors: Guillaume Bolbenes, Jean-Paul Georges Poncelet
  • Patent number: 10489081
    Abstract: A method for reducing coordination times in asynchronous data replication environments is disclosed. In one embodiment, such a method includes providing multiple primary storage devices in an asynchronous data replication environment. A command is issued, to each of the primary storage devices, to begin queuing I/O in order to coordinate a consistency group. Each primary storage device receives the command. The method further calculates, for each of the primary storage devices, an amount of time to wait before executing the command with the objective that each primary storage device executes the command at substantially the same time. Each primary storage device is configured to execute the command after receiving and waiting its corresponding amount of time. A corresponding system and computer program product are also disclosed herein.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Gregory E. McBride, Matthew J. Ward
  • Patent number: 10482014
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine that an information handling system is to be powered down and provide, to a non-volatile memory medium via a power coupling of the non-volatile memory medium, information indicating that the non-volatile memory medium is to be powered down. For example, the power coupling of the non-volatile storage medium may include one or more conductors, and the information indicating that the non-volatile memory medium is to be powered down may be provided via at least one of the one or more conductors. In one or more embodiments, the non-volatile memory medium may include volatile storage and non-volatile storage. For example, based at least on the information indicating that the non-volatile memory medium is to be powered down, the non-volatile memory medium may store information, that is stored by the volatile storage, via the non-volatile storage.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 19, 2019
    Assignee: Dell Products L.P.
    Inventors: Kan Lip Vui, Shun-tang Hsu
  • Patent number: 10482019
    Abstract: Proposed are a storage apparatus and a control method thereof capable of improving the response performance to a read access of various access patterns. When data to be read is not retained in a data buffer memory, upon staging the data to be read, a processor performs sequential learning of respectively observing an access pattern in units of blocks of a predetermined size and an access pattern in units of slots configured from a plurality of the blocks regarding an access pattern of the read access from the host apparatus, and expands a data range to be staged as needed based on a learning result of the sequential learning.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 19, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Taku Adachi, Hisaharu Takeuchi
  • Patent number: 10482049
    Abstract: Configuring NVMe devices for redundancy and scaling includes: identifying, by a first SSD (‘Solid State Drive’) driver executing on a first CPU (‘Central Processing Unit’), address space of a first SSD coupled to the first CPU by a first PCI (‘Peripheral Component Interconnect’) switch, the first PCI switch including one or more non-transparent bridges (‘NTBs’); partitioning, by the first SSD driver, the address space of the first SSD amongst the NTBs of the first PCI switch and the first CPU, where each NTB is configured to translate CPU memory addresses received from a CPU into a drive address in the address space partitioned to the NTB; and partitioning, by the first SSD driver, a plurality of namespaces of the first SSD amongst the first CPU and the NTBs.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Patrick L. Caporale, Randolph S. Kolvick, Pravin Patel, Gregory B. Pruett, Theodore B. Vojnovich
  • Patent number: 10474394
    Abstract: Example methods are provided to perform persistent reservation emulation in a shared virtual storage environment that includes a first host supporting a first node and a second host supporting a second node. One example method may comprise detecting a command issued by a first node to command issued by a first node to update information relating to a reservation or registration associated with a virtual disk, and updating persistent reservation information associated with the virtual disk to indicate that the command has been issued by the first node. The method may also comprise determining that the second node either has acknowledged the updated persistent reservation information, or has not acknowledged the updated persistent reservation information within a time interval. The method may further comprise updating the persistent reservation information based on the command.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 12, 2019
    Assignee: VMWARE, INC.
    Inventors: Rahul Dev, Gautham Swamy, Prasanna Aithal
  • Patent number: 10459824
    Abstract: Performing a cache-based trace recording using cache coherence protocol (CCP) data. Embodiments detect that an operation that causes an interaction between a cache line and a backing store has occurred, that logging is enabled for a processing unit that caused the operation, that the cache line is a participant in logging, and that the CCP indicates that there is data to be logged to a trace. Embodiments then cause that data to be logged to the trace, which data is usable to replay the operation.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 10452321
    Abstract: A storage system has a cluster structure in which a node is connected with a different node, the node having a volatile memory for storing first update data from a host and a first non-volatile memory for storing second copy data of second update data from the host to the different node, and having a copy management processing unit for storing first copy data of the first update data into a second non-volatile memory of the different node, and a storage service processing unit for transmitting, to the host, a response with respect to an update request of the first update data in response to the storage of the first copy data of the first update data by the copy management processing unit into the second non-volatile memory of the different node.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Hayasaka, Kazumasa Matsubara, Masanori Takada, Yoshihiro Yoshii