Abstract: A system linearization assembly generally includes a delay device that receives an input signal from a signal source and delays the input signal by a predetermined delay function. An attenuation device receives a modified output signal from a signal modifying device, wherein the output signal is based on the input signal and includes a time varying parameter representing a plurality of frequency components including at least one component caused by non-linear intermodulation distortion. The attenuation device attenuates the output signal by a factor that is equal to at least one parameter of the modifying device. A computing device compares the attenuated output signal with the delayed input signal to obtain a resultant signal that includes the component caused by non-linear intermodulation distortion. A detection device detects at least one parameter of the resultant signal. Based on the detected parameter, a controller facilitates a modification of the component.

Abstract: In one embodiment, a circuit comprises a power amplifier. The circuit further comprises a memory that stores bias current values corresponding to a plurality of frequencies across a frequency band for setting the bias of a power amplifier based on selected frequencies, and a controller configured to provide at least one bias current value corresponding to a selected frequency from the memory to the power amplifier in response to a frequency selection signal. The bias current value at each frequency may be selected to maximize power efficiency or minimize adjacent channel leakage-power ratio of the power amplifier at said frequency. In one embodiment, the memory further stores bias current values corresponding to the plurality of frequencies across the frequency band at a plurality of temperatures for setting the bias of a power amplifier based on a temperature of the power amplifier and on selected frequencies.

Abstract: Consumption current may be reduced in a power amplifier module in which a power supply voltage supplied to a power amplification transistor is controlled according to the level of output power. The power amplifier module includes an amplification transistor supplied with the power supply voltage according to the level of output power to amplify a radio-frequency signal, a bias control circuit for generating a bias voltage according to the power supply voltage, and a bias circuit for supplying a bias current according to the bias voltage to the amplification transistor, wherein current flowing through the amplification transistor when the radio-frequency signal is not input is varied according to the level of output power.

Abstract: Disclosed is an amplifier circuit having an output stage that includes an H-bridge circuit. The H-bridge circuit includes sense resistors on one side of the circuit. A current detection circuit can produce an output indicative of current flow through a load based on voltages across the sense resistors.

Abstract: The current-mode folding amplifier is a current-mode saw-tooth folding amplifier having a minimal number of current mirrors in the signal path from input to output. This minimizes the delays imposed by current mirrors on the speed of the amplifier. The amplifier has a full scale delay of 5.9 ns. The operation of the amplifier is verified in simulation using LFoundry 150 nm process in Cadence Tools.

Abstract: A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.

Abstract: According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network.

Abstract: An amplifier comprises a main-amplifier circuit, an auxiliary-amplifier circuit and a signal-generating device. Output terminals of the main-amplifier circuit and of the auxiliary-amplifier circuit are connected according to the Doherty principle. The signal-generating device is configured to generate directly a main-amplifier signal as an input signal of the main-amplifier circuit and an auxiliary-amplifier signal as an input signal of the auxiliary-amplifier circuit.

Abstract: A power amplifier includes an input circuit configured to receive an input signal. At least two transistors connected in series. A first transistor of the at least two transistors is located at a first end of the at least two transistors. A second transistor of the at least two transistors is located at a second end of the at least two transistors. The first transistor is coupled to a low voltage power supply node. The first gate of the first transistor is coupled to a first bias voltage. The input signal is coupled to a first gate of the first transistor. At least one capacitor is coupled between a second gate of the second transistor and the low voltage power supply node. An output circuit coupled to a second gate of the second transistor.

Abstract: A multiple-series amplifying device (100) of the present invention includes multiple series of amplifiers (110, 120) which are formed in parallel so as to input and output signals individually. Each of multiple-series of amplifiers (110, 120) includes a plurality of semiconductor amplifying elements (111, 112, 121, 122) which are driven in parallel so as to amplify signals. A pair of semiconductor amplifying elements (112, 121) adjoining together in a pair of amplifiers (110, 120) is formed in a single package (130).

Abstract: A circuit having a first transistor being a common gate connected transistor and a second transistor, the second transistor being M times the size of the first transistor, the first and second transistors having commonly connected gates and commonly connected drains, wherein an apparatus is provided to regulate the source voltage of the second transistor to track the source voltage of the first transistor, wherein the current gain of the circuit is M+1.

Abstract: Digital envelope tracking with multilevel supply voltages is performed for wide-bandwidth signals. A digital control component generates a digital control code that facilitates switching of resistor values of one or more resistors coupled between a power amplifier and a supply voltage of plurality of supply voltages. A driver component supplies an envelope voltage of the plurality of supply voltages for the power amplifier as a function of the digital control code.

Abstract: In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current iH flowing as a single bias current iB=iH flows into the first stage. A single pull-down current iT sources to ground from the second stage, wherein iH=iT=iB substantially. In certain embodiments, the transconductance of the second stage may be increased by providing two transconductors coupled at their base nodes.

Abstract: A system linearization assembly generally includes a filter that is coupled to a measuring device. The filter is configured to receive a signal that includes a time varying parameter representing a plurality of frequency components including at least one component caused by non-linear intermodulation distortion, such as an odd-order intermodulation distortion component. The filter is also configured to isolate at least one harmonic of the frequency components with the same order as the component caused by non-linear intermodulation distortion. The measuring device is configured to measure at least one parameter of the isolated harmonic. The system linearization assembly also includes a controller coupled to the measuring device. The controller is configured to modify, for example by minimizing, the signal from the determined measurement to facilitate a modification, such as a reduction, of the component caused by non-linear intermodulation distortion.

Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Abstract: Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

Abstract: A digital predistortion apparatus comprising: a nonlinear device; a memory effect compensator; a constant value characteristic acquirer; a cost function generator; and a coefficient updater is described.

Abstract: Presented are circuits and methods for providing real-time short-circuit detection, capable of detecting a short-circuit prior to occurrence of an over-limit current event. Such a circuit can be used to provide real-time short-circuit detection for a switched-mode system for a switched-mode system having a pre-driver and a power stage, and includes a reference block for generating a reference voltage according to drive signals provided by the pre-driver, and a comparator, which may be a synchronized comparator. The comparator is configured to compare the reference voltage to a switching node voltage generated in a power stage of the switched-mode system, and to produce an output enabling detection of the short-circuit in the switched-mode system.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A microwave integrated circuit includes a substrate and a power amplifier on the substrate. The power amplifier includes a power divider circuit having an input configured to receive an input RF signal, a base amplifier having an input coupled to a first output of the power divider circuit and a peaking amplifier having an input coupled to a second output of the power divider circuit and an output coupled to an output combining node. The power amplifier further includes an impedance inverter circuit coupling the output of the base amplifier to the output combining node and a load matching circuit having an input coupled to the output combining node and an output configured to be coupled to a load.