Abstract: Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.

Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.

Abstract: An amplifier circuit includes: plural transistors; plural first transmission lines respectively connected between input terminals of the plural transistors; plural second transmission lines respectively connected between output terminals of the plural transistors; an input node connected to the input terminal of a first stage transistor among the plural transistors; an output node connected to the output terminal of a final stage transistor among the plural transistors; and a capacitance connected to the output terminal of the first stage transistor via a third transmission line.

Abstract: It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level ?. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power Pm and a second signal having a power Pa, a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value ?, wherein ??<?<?. The amplifier arrangement further comprises a combining network.

Abstract: Apparatus and methods for power amplifier bias circuits are disclosed herein. In certain implementations, a power amplifier bias circuit includes a current source configured to generate a reference current, a plurality of reference bipolar transistors, a selection circuit configured to select one or more selected reference bipolar transistors from the plurality of reference bipolar transistors, and a transimpedance amplifier. The one or more selected reference bipolar transistors have a current therethrough that changes in relation to a power amplifier stage bias voltage, and the transimpedance amplifier is configured to control the power amplifier stage bias voltage based on an error current corresponding to a difference between the reference current and the current through the one or more selected reference bipolar transistors.

Abstract: Disclosed are apparatuses and methods to overcome technology limitations to achieve linearity and efficiency performance suitable for practical wireless communications systems. In an embodiment, an amplifier is provided that superimposes the transconductance from a common source amplifier with inductor degeneration with the transconductance from a common source amplifier without degeneration. In an embodiment, an amplifier is provided having a feedback-balun-transformer that provides electro-magnetic coupling between primary, secondary, and negative feedback degeneration inductors and a differential to single-ended conversion output.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: A distributed amplifier includes a plurality of transistors, a first line connecting gate electrodes of the transistors to each other, and a second line connecting drain electrodes of the transistors to each other, wherein the first line and the second line are electromagnetically coupled to each other at a position situated between immediately adjacent transistors among the plurality of transistors.

Abstract: Circuitry includes a balanced amplifier and bias adjustment circuitry. The bias adjustment circuitry is coupled to the balanced amplifier and is configured to measure an RF termination voltage across an output termination impedance of the balanced amplifier and adjust a bias voltage supplied to the balanced amplifier based on the RF termination voltage. Notably, the RF termination voltage is proportional to a voltage standing wave ratio (VSWR) of the balanced amplifier, and thus enables an accurate measurement thereof. By using the RF termination voltage to adjust a bias voltage supplied to the balanced amplifier, overvoltage and/or thermally stressing conditions of the balanced amplifier as a result of high VSWR may be avoided while simultaneously avoiding the need for large or expensive isolation circuitry.

Abstract: A microwave generator and power amplifier system for the same are provided. The power amplifier system can include a first power amplifier unit that can receive an input power signal and can provide an output power signal. A power splitter unit can receive the output power signal and can generate a plurality of split power input signals. The split power input signals can be received by a second power amplifier unit that can provide a plurality of split power output signals. At least one isolator unit that can couple at least part of the second power amplifier unit with a power combiner unit. The power combiner unit can receive the plurality of split power output signals from the second power amplifier unit via the at least one isolator unit and can combine the plurality of split power output signals into a unified power output.

Abstract: The present application provides a multiband power amplification apparatus. The first input terminal receives a signal in a frequency band f1; the second input terminal receives a signal in a frequency band f2. The first adjustment module adjusts a first channel of signal and then outputs an adjusted first channel of signal to the first adder. The second adjustment module adjusts a third channel of signal and then outputs an adjusted third channel of signal to the first adder. The first adder converges the signal adjusted by the second adjustment module and the signal output by the first adjustment module and then outputs a converged signal to a first digital-to-analog converter. The second adder converges a second channel of signal and a fourth channel of signal and then outputs a converged signal to a second digital-to-analog converter.

Abstract: An amplifying system with increased linearity is disclosed. The amplifying system includes a first gain stage with a first gain characteristic, a second gain stage with a second gain characteristic, and bias circuitry configured to substantially maintain alignment of distortion inflection points between the first gain characteristic and the second gain characteristic during operation. The bias circuitry is configured to further maintain alignment of the distortion inflection points between the first gain characteristic and the second gain characteristic over design corners by providing substantially constant headroom between quiescent bias voltage and turnoff of the first gain stage and the second gain stage. In some embodiments the first gain characteristic is expansive and the second gain characteristic is compressive. In other embodiments the first gain characteristic is compressive and the second gain characteristic is expansive.

Abstract: The feed reflected Doherty amplifier utilizes the output characteristics of the carrier amplifier to control the input signal of the peaking amplifier to improve the gain, linearity and efficiency of a Doherty amplifier. The feed reflected Doherty amplifier comprises an input power splitter, a carrier amplifier branch and a peaking amplifier branch combined into a common load, an output directional coupler and an input directional coupler connected via a phase shift element.

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

Abstract: A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

Abstract: The disclosure relates to an enhanced Doherty amplifier that provides significant performance improvements over conventional Doherty amplifiers. The enhanced Doherty amplifier includes a power splitter, combining node, a carrier path, and a peaking path. The power splitter is configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output. The carrier path includes carrier power amplifier circuitry, a carrier input network coupled between the carrier splitter output and the carrier power amplifier circuitry, and a carrier output network coupled between the carrier power amplifier circuitry and the Doherty combining node.

Abstract: An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well.

Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.

Abstract: Apparatus and method for an output stage of an amplifier are disclosed. A current source circuit provides current to a transistor connected to the amplifier output node to produce output voltage, and the current source circuit has two current mirror paths, one of which replicates the output voltage at the output node. As the output voltage approaches rail, more current is steered to the current mirror path not replicating the output voltage and provides additional current or voltage necessary to keep the current source circuit operational.

Abstract: Aspects of the present invention include a circuit that includes an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other. The circuit further includes an actual switched amplification stage configured to direct one of the balun output signals to a phase inverter output, and a replica switched amplification stage connected in parallel with the actual switched amplification stage, wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit.