Patents Examined by Hieu P Nguyen
  • Patent number: 11290061
    Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: March 29, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chia-Wei Su, Ju-Lin Huang, Keko-Chun Liang
  • Patent number: 11290075
    Abstract: An operational amplifier includes a differential amplification circuit configured to receive and amplify an input voltage to generate an output voltage, and receive a feedback signal, and the feedback signal adjusts a common-mode voltage of the output voltage, a reference voltage generation circuit configured to detect status information of the operational amplifier, and generate a reference voltage based on the status information, where the status information includes a temperature or an operating voltage of the operational amplifier, and a common-mode feedback circuit configured to receive the output voltage and the reference voltage, and provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 29, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Haixi Li
  • Patent number: 11290071
    Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: March 29, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Cory J. Peterson, Anand Ilango, Eric Kimball
  • Patent number: 11277104
    Abstract: A dynamically stabilizable amplifier drives an output current into an RLC load. A driver stage generates the output current, and a control circuit compares a current level of the amplifier output with a threshold and selectively enables a stabilizing resistor (to selectively shunt the load or dampen in series with the load, depending on RLC load type) at the driver stage output based on the comparison so that the amplifier is stable across a range of the output current level. The control circuit disables the resistor when the output current is above the highest threshold and enables it when below. The control circuit may control the resistor to have one of multiple resistance values based on a comparison with multiple thresholds. The output current level may be determined by replicating the output current level or by an input current level that sets the output current level independent of the load.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 15, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Vamsikrishna Parupalli, John L. Melanson
  • Patent number: 11277100
    Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 15, 2022
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
  • Patent number: 11277101
    Abstract: The present disclosure provides a current-to-voltage signal converter which may operate at an adjusted voltage. The current-to-voltage converter includes a trans-impedance amplifier which converts a current input into a voltage output. The voltage output may operate around an undesirable predetermined voltage, and must therefore be adjusted in order to make it suitable for any downstream signal processing circuitry, such as an ADC. As such, a subtractor circuit is coupled to the output of the trans-impedance amplifier. At the input of the subtractor circuit, a voltage adjustment circuit is employed, to adjust the voltage input to the subtractor circuit. As such, the input to the subtractor is adjusted between a first predetermined voltage threshold and a second predetermined voltage threshold, and the subtractor circuit may therefore be a low-voltage component.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: March 15, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jun Gao, Tony Liu, Sharad Vijaykumar
  • Patent number: 11271532
    Abstract: This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 8, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11264955
    Abstract: A semiconductor amplifier circuit has a driver that outputs a drive signal corresponding to an input signal and switches drive capability of the drive signal in accordance with a logic of an instruction signal, an instruction signal setting unit that sets the logic of the instruction signal in accordance with whether the input signal satisfies a predetermined condition, and an output circuit that comprises a control terminal to which the drive signal is input and an output terminal that outputs a signal obtained by amplifying the input signal.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Akio Ogura
  • Patent number: 11264960
    Abstract: A current source circuit can include a first amplifier circuit and a second amplifier circuit. Each of the first and second amplifier circuits can be configured to generate respective amplifier output voltages based on a corresponding input voltage and respective feedback voltage. The current source circuit can further include a cross-coupling circuit that can include a first set of resistors and a second set of resistors. The first set of resistors can be configured to establish a first cross-coupling voltage based on the first amplifier output voltage and the second set of resistors can be configured to establish a second cross-coupling voltage based on the second amplifier output voltage. The first and second amplifier circuits can be configured to maintain the first and second cross-coupling voltage at a given voltage amplitude to provide a constant current at an output node of the current source circuit.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 1, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Sunny Bagga, Brian J. Cadwell, Shaun Mark Goodwin, Scott F. Allwine
  • Patent number: 11264957
    Abstract: The present invention generally relates to a structure and method of audio amplifier by dynamic impedance adjustment, including a power amplifying unit, a loud-speaker, a current sensing unit and a subtraction unit. The power amplifying unit has a fixed closed loop gain, with an input side and an output side; the loud-speaker is electrically connected to the output side of the power amplifying unit; the current sensing unit senses the output current of the power amplifying unit, and the sensed output current is converted into a current control voltage signal; the subtraction unit inputs the audio voltage signal and the feedback current control voltage signal, and outputs the difference of the audio voltage signal minus the current control voltage signal, and inputs it to the input side of the power amplifying unit. The output sound quality of the loud-speaker is improved by dynamic impedance adjustment.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 1, 2022
    Inventor: Chung-Fu Chou
  • Patent number: 11264956
    Abstract: A DC offset cancellation circuit and a DC offset cancellation method are disclosed. The DC offset cancellation circuit comprises a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter. The high-speed amplifier comprises an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage. The voltage comparator is connected to the output buffer stage. The microprocessor is connected to the voltage comparator. The digital-to-analog converter is connected to the microprocessor. The digital-to-analog converter is connected to the input stage.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 1, 2022
    Assignee: XIAMEN UX HIGH-SPEED IC CO., LTD.
    Inventors: Kexun Zhang, Junhua Ge, Jie Zhou, Jianhua Pan
  • Patent number: 11258411
    Abstract: A Class D amplifier having an integrating primary amplifier with an internal feedback, the amplifier further comprising a feedback loop with a filter of at least second order.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 22, 2022
    Assignee: PURIFI APS
    Inventors: Bruno Putzeys, Lars Risbo
  • Patent number: 11251760
    Abstract: Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Analog Devices, Inc.
    Inventor: Yoshinori Kusuda
  • Patent number: 11249499
    Abstract: A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 15, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Alexander Kurylak, Bibhu Prasad Das, Kadaba Lakshmikumar
  • Patent number: 11251754
    Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Noemi Gallo, Edoardo Botti
  • Patent number: 11245368
    Abstract: A class D amplifier includes a self-oscillating class D amplification circuit that is driven by an output current signal; and a voltage-current converting circuit that outputs an output current signal in response to an input signal voltage and an output signal voltage from a feedback signal voltage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: February 8, 2022
    Assignee: Yamaha Corporation
    Inventors: Takeshi Togawa, Masao Noro
  • Patent number: 11239803
    Abstract: Various methods and circuital arrangements for protection of an RF amplifier are presented. According to one aspect, the RF amplifier is part of switchable RF paths that may include at least one path with one or more attenuators or switches that can be used during normal operation to define different modes of operation of the at least one path. An RF level detector monitors a level of an RF signal during operation of any one of the switchable RF paths and may control the attenuators or switches to provide an attenuation of the RF signal according to a desired level of protection at an input and/or output of the RF amplifier. According to another aspect, the RF level detector may control a switch to force the RF signal through a different switchable RF path.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 1, 2022
    Assignee: PSEMI CORPORATION
    Inventors: Parvez Daruwalla, David Kovac
  • Patent number: 11239806
    Abstract: An ultra-low power sub-threshold gm stage is disclosed where transconductance is very stable with process, temperature, and voltage variations. This technique can be implemented in a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain can achieve a small temperature coefficient of 48.6 ppm/° C. and exhibits small sigma of 75 mdB with process. The second order biquad can achieve temperature stability of 69 ppm/° C. and a voltage coefficient of only 49 ppm/mV.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 1, 2022
    Assignee: Northeastern University
    Inventor: Aatmesh Shrivastava
  • Patent number: 11228284
    Abstract: A method for controlling one or more parameters of an amplifier system may include receiving an indication of a physical quantity associated with the amplifier system, determining one or more parameters of the amplifier system in response to the indication, and causing the amplifier system to operate in accordance with the one or more parameters.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric Lindemann, Itisha Tyagi
  • Patent number: 11228286
    Abstract: A linear amplifier outputs differential signals corresponding to differential signals input to a first signal input terminal and a second signal input terminal, and includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third transistor, a fourth transistor, a differential amplifier, and a signal processing circuit. The signal processing circuit includes a first transistor and a second transistor, and includes a resistor as a common voltage output part that outputs a common voltage. The differential amplifier receives the common voltage and a reference voltage, and applies a voltage corresponding to the voltage difference between the common voltage and the reference voltage to the control terminals of the transistors.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 18, 2022
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Hideyuki Kokatsu