Abstract: Headset assemblies and headset connectors are provided. Headset connectors can include a magnetic mating face and a plurality of electrical contacts disposed within the mating face. Engaging assemblies and engaging connectors are also provided. The engaging connectors can include a housing having a mating side, a magnetic array structure, and a plurality of spring biased contact members. The magnetic array structure can be fixed within the housing and house a plurality of spring biased contact members. The spring biased contact members can include tips that extend out of the mating side. The tips can electrically couple with electrical contacts in a headset connector.

Abstract: A marking method is provided for putting markings on the surface of a packaged semiconductor device. The semiconductor device includes a semiconductor chip and a resin package for covering the semiconductor chip. The method includes the steps of forming a groove in the obverse surface of the resin package, and filling the groove with a resin that is visually distinguishable from the resin package.

Abstract: Carriers enabling multichip driving of optoelectronic interconnects are disclosed. In one instance, the carriers provide a substantially perpendicular interface between the host circuit board and the optoelectronic die.

Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.

Abstract: A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

Abstract: Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.

Abstract: An assembly of nanoelements forms a three-dimensional nanoscale circuit interconnect for use in microelectronic devices. A process for producing the circuit interconnect includes using dielectrophoresis by applying an electrical field across a gap between vertically displaced non-coplanar microelectrodes in the presence of a liquid suspension of nanoelements such as nanoparticles or single-walled carbon nanotubes to form a nanoelement bridge connecting the microelectrodes. The assembly process can be carried out at room temperature, is compatible with conventional semiconductor fabrication, and has a high yield. The current-voltage curves obtained from the nanoelement bridge demonstrate that the assembly is functional with a resistance of ?40 ohms for gold nanoparticles. The method is suitable for making high density three-dimensional circuit interconnects, vertically integrated nanosensors, and for in-line testing of manufactured conductive nanoelements.

Abstract: Multi-chip quad flat no-lead (QFN) packages and methods for making the same are disclosed. A multi-chip package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die mounted on the first die and including a plurality of second bond pads, wherein selected second bond pads are wire-bonded to a second side, opposite the first side, of the leadframe. Another package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die flip-chip mounted on a second side of the leadframe and including a plurality of second bond pads, wherein selected second bond pads are bonded to the second side of the leadframe. Other embodiments are also described.

Abstract: A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.

Abstract: A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape.

Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.

Abstract: An integrated circuit includes a substrate and a first integrated circuit die having a first circuit coupled to the substrate via a first bonding wire, the first circuit having a first intra-chip interface. A second integrated circuit die has a second circuit coupled to the substrate via a second bonding wire, the second circuit having a second intra-chip interface, the second bonding wire electrically isolated from the first bonding wire. The first circuit communicates with the second circuit via the first intra-chip interface and the second intra-chip interface, and wherein the first intra-chip interface and the second intra-chip interface communicate via a first electromagnetic coupling between the first bonding wire and the second bonding wire.

Abstract: The present invention provides a wafer (3) comprising a through-wafer via (7) through the wafer (3) formed by a through-wafer via hole (9) and at least a first conductive coating (25). A substantially vertical sidewall (11) of the through-wafer via hole (9) except for a constriction (23) provides a reliable through-wafer via (7) occupying a small area on the wafer. The wafer (3) is preferably made of a semiconductor material, such as silicon, or a glass ceramic. A method for manufacturing such a wafer (3) is described.

Abstract: A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

Abstract: A display device is provided with a pair of a first electrode and a second electrode, at least one electrode of the first and second electrodes being transparent or translucent and a phosphor layer provided as being sandwiched between the first electrode and the second electrode, and at least one buffer layer provided as being sandwiched between the first or second electrode and the phosphor layer, and the phosphor layer has a plurality of pixel regions that are selectively allowed to emit light in a predetermined range thereof and non-pixel regions that divide at least one portion of the pixel regions, and wherein the buffer layer is sandwiched between the first or second electrode and the phosphor layer so that the size of an electric potential barrier between the first or second electrode and the phosphor layer via the buffer layer is made smaller than the size of a Schottky barrier between the first or second electrode and the phosphor layer that are directly made contact with each other without the buffe

Abstract: A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.

Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract: An assembly includes a support element and a chip having contact elements. The chip is mounted onto the support element with the contact elements facing the support element. A shield layer is on the support element for electrically or magnetically shielding a circuit element of the chip.

Abstract: An earphone includes a body with a surrounding side, a rotatable loop and an ear hook. The rotatable loop is pivotally connected with the body on two opposite ends of the surrounding side. The body and the rotatable loop can rotate with respect to a first axis and with respect to each other. The ear hook is pivotally mounted on one side of the rotatable loop near where the rotatable loop is connected with the body, and the ear hook can rotate with respect to a second axis, which is different from the first axis.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer.