Patents Examined by Hoa B. Trinh
  • Semiconductor device and method of manufacturing same
    Patent number: 8624235
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • On-Chip RF shields with front side redistribution lines
    Patent number: 8617929
    Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Jenei Snezana
  • Thin semiconductor die package
    Patent number: 8618675
    Abstract: A semiconductor die is attached to a substrate by a glass frit layer. Gas that might be trapped between the die and the glass frit layer during firing of the glass frit can escape through passages that are formed against the bottom surface of the die by topographies that extend away from and which are substantially orthogonal to the bottom of the die.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: December 31, 2013
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Xiaoyi Ding, Jeffrey James Frye
  • Stacked integrated circuit package-in-package system and method of manufacture thereof
    Patent number: 8617924
    Abstract: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: OhSug Kim, Jong-Woo Ha, Jong Wook Ju
  • RFID tags with bumped substrate, and apparatuses and methods for making
    Patent number: 8614506
    Abstract: Radio Frequency Identification (RFID) tags are provided, along with apparatuses and methods for making. In some embodiments, the RFID tags include an RFID tag chip that is attached to an inlay and/or a strap. The inlay or strap has one or more contact bumps formed thereon. In some of these embodiments, the RFID tag chip includes pads for electrical contacts, but not chip-bumps, thanks to the contact bump.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: December 24, 2013
    Assignee: Impinj, Inc.
    Inventors: Jay M. Fassett, Ernest Allen, III, Ronald L. Koepp, Ronald A. Oliver, Steven I. Mozsgai
  • Single piece earloop with corresponding pivot post
    Patent number: 8611582
    Abstract: In an earloop headset or earphone or other ear-mounted audio device, a housing is attached to an earloop by providing a ball and complementary socket arrangement between the earloop and a pivot post secured to the housing. The earloop or pivot post are made of an elastomeric material to allow the earloop and pivot post to each be made of a single piece of material and be clipped into engagement after manufacture.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 17, 2013
    Assignee: Plantronics, Inc.
    Inventor: Barry J Lee
  • Wide band and radio frequency waveguide and hybrid integration in a silicon package
    Patent number: 8587106
    Abstract: A device includes a device wafer having a circuit component formed thereon and having vias formed therein and a cap wafer bonded to the device wafer. The cap wafer has a cavity therein. The cavity has a post formed therein, and the post is positioned to mechanically support the vias formed in the device wafer. The cavity has a volume, the volume substantially enclosing the circuit component formed on the device wafer. The cavity has a width and height such that an impedance of a transmission line is dependent upon the width and height of the cavity, or the impedance of a transmission line is dependent upon the width of a center conductor within the cavity.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: November 19, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, Jeremy Muldavin, Peter W. Wyatt, Craig L. Keast, Steven Rabe
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 8575764
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Semiconductor device, and inspection method thereof
    Patent number: 8552549
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Masatoshi Shinagawa, Takeshi Kawabata
  • Earphone having an articulated acoustic tube
    Patent number: 8553923
    Abstract: An in-ear earphone has a housing in which a driver is located. An articulated acoustic tube is coupled to the housing at its near end portion. The acoustic tube has an open far end portion that is to be inserted into an ear. A hinge or pivot mechanism is formed in the tube, between the near and far end portions. An acoustic aperture formed within the mechanism acoustically couples sound pressure waves, generated by the driver, to the far end portion of the acoustic tube. Other embodiments are also described.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: October 8, 2013
    Assignee: Apple Inc.
    Inventors: Victor M. Tiscareno, Michael B. Hailey
  • System for clamping heat sink
    Patent number: 8546192
    Abstract: A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Harman International Industries, Incorporated
    Inventor: Greg Mlotkowski
  • Electronic device package and method for fabricating the same
    Patent number: 8541877
    Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 24, 2013
    Inventors: Chia-Lun Tsai, Ching-Yu Ni, Tien-Hao Huang, Chia-Ming Cheng, Wen-Cheng Chien, Nan-Chun Lin, Wei-Ming Chen, Shu-Ming Chang, Bai-Yao Lou
  • Semiconductor device, method of manufacturing the semiconductor device, flip chip package having the semiconductor device and method of manufacturing the flip chip package
    Patent number: 8530275
    Abstract: A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Young Lee, You-Seung Jin, Geon-Woo Park
  • Method of electrically connecting a microelectronic component
    Patent number: 8513799
    Abstract: A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the support structure, and the top surfaces can be substantially coplanar with one another. A microelectronic device having a surface with bond pads can overlie the second surface of the support structure with the bond pad-bearing surface of the microelectronic device facing toward the support structure. Connections can electrically connect the posts with the bond pads.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: August 20, 2013
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Package substrate structure and chip package structure and manufacturing process thereof
    Patent number: 8513820
    Abstract: A chip package structure includes a substrate, chips and an elastic element. The substrate has a first surface, a second surface, a first patterned metal layer on the first surface and a second patterned metal layer on the second surface, wherein the substrate is suitable for being clipped between an upper mold chase and a lower mold chase of a package mold. The chips are disposed on the first surface, wherein the chips are suitable for being contained in containing spaces defined by the upper mold chase and the substrate. The elastic element is disposed on the second surface and surrounds the second patterned metal layer, wherein the elastic element is suitable for contacting the lower mold chase and is located between the lower mold chase and the substrate. In addition, a manufacturing process of the chip package and a package substrate structure are also provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 20, 2013
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Wen-Chieh Tsou
  • Semiconductor device and method for manufacturing the same
    Patent number: 8513088
    Abstract: In one embodiment, an adhesive layer is formed by applying a liquid adhesive to a semiconductor wafer whose wafer shape is maintained by a surface protective film attached to a first surface. A supporting sheet having a tacky layer is attached to a second surface of the semiconductor wafer. After the surface protective film is peeled, the supporting sheet is expanded to cleave the adhesive layer including the adhesive filled into the dicing grooves. The first surface of the semiconductor wafer is cleaned while an expansion state of the supporting sheet is maintained. Tack strength of portions corresponding to the dicing grooves of the tacky layer is selectively reduced before cleaning.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Fumihiro Iwami
  • Co-axial restraint for connectors within flip-chip packages
    Patent number: 8507325
    Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons
  • Method for manufacturing semiconductor device, and semiconductor device
    Patent number: 8502379
    Abstract: A semiconductor device includes an insulating film base member and a wiring pattern that is formed on the insulating film base member. The wiring pattern has a surface, with at least a peripheral section of the surface being a peeled surface of the wiring pattern peeled from the insulating film base member. The semiconductor device further includes a plating layer that covers the surface of the wiring pattern, and an IC chip that has an active surface with a bump bonded to the wiring pattern. The peeled surface of the wiring pattern is peeled from the insulating film base member around a bonding position of the wiring pattern bonded with the bump.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 6, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Shigehisa Tajimi
  • Multi-stacked semiconductor dice scale package structure and method of manufacturing same
    Patent number: 8502394
    Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 6, 2013
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Kim-Yong Goh
  • Double-faced electrode package, and its manufacturing method
    Patent number: 8501542
    Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 6, 2013
    Assignee: Oki Semiconductor Co., Ltd
    Inventors: Masamichi Ishihara, Harufumi Kobayashi