Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Abstract: According to one embodiment, a printed wiring board structure comprises a printed wiring board having first and second component mounting surfaces at front and back sides thereof, respectively, each for mounting a semiconductor package loading a semiconductor chip loaded on a substrate as a mounting component, a first semiconductor package mounted on the first component mounting surface, and a second semiconductor package mounted on the second component mounting surface, wherein the first and second semiconductor packages have a positional relationship such that the substrates are partially overlapped via the printed wiring board, and the semiconductor chips are not overlapped.

Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Abstract: A semiconductor light emitting device comprises a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer is adapted to emit first light having a first peak wavelength. A first wavelength converting material is adapted to absorb the first light and emit second light having a second peak wavelength. A second wavelength converting material is adapted to absorb either the first light or the second light and emit third light having a third peak wavelength. A filter is adapted to reflect fourth light having a fourth peak wavelength. The fourth light is either a portion of the second light or a portion of the third light. The filter is configured to transmit light having a peak wavelength longer or shorter than the fourth peak wavelength. The filter is disposed over the light emitting device in the path of at least a portion of the first, second, and third light.

Abstract: According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/mK. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater.

Abstract: A method for manufacturing a semiconductor device includes: when bonding a bump of an IC chip to a bonding position of a wiring pattern that is formed on an insulating film base member and has a surface covered by a plating layer, forming a plating layer around the bonding position among the wiring pattern at least in an outer peripheral section of a peeled surface of a portion of the wiring pattern peeled from the film base member.

Abstract: A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.

Abstract: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm?2. A GaN single crystal production method includes introducing group III and V raw material gases on a substrate, and growing a GaN single crystal on the substrate. The growth temperature is within the range of not less than 1100° C. and not more than 1400° C., the group V to III raw material gas partial pressure ratio (V/III ratio) is within the range of not less than 0.4 and not more than 1, and the number density of polarity inversion zones in a surface of the substrate is not more than 20 cm?2.

Abstract: The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |VDS| of the transistor is set equal to or larger than 1 V and equal to or less than |VGS?Vth|. The transistor is used as a resistor so that the resistance of a light emitting element can be held by the transistor. This slows down an increase in internal resistance of the light emitting element and the resultant current value reduction. Accordingly, a change with time in light emission luminance is reduced and the reliability is improved.

Abstract: In one embodiment, an integrated circuit device includes an active area encompassed by a seal ring. The seal ring may include a deep moat formed on an outer edge of the seal ring. The deep moat may have a depth that extends substantially to the substrate to prevent cracks from propagating into the active area. Alternatively or in addition, the seal ring may include redundant vias.

Abstract: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask layer to form a projection electrode of the second metal; and removing the stopper mask layer after the metal supplying step.

Abstract: Check valve package for pb-free, single piece electronic modules, the package having an exterior and an interior, and at least one electronic device mounted within the interior of the package electrically connected to a lead-free solder ball grid array on a surface of the package, the package having a check valve between the interior and exterior of the package configured to allow flow from the interior to the exterior and to prevent flow form the exterior to the interior. The package withstands the solder reflow temperatures for the reflow of the pb-free solder balls of a ball grid array packaging of an NVSRAM during mounting on a circuit board. The package is suitable for packaging circuits containing rechargeable batteries and for packaging other electronic devices.

Abstract: The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

Abstract: A prefabricated lead frame to bond a chip and a substrate, and a bonding method using the prefabricated lead frame. The prefabricated lead frame includes an inner ring, an outer ring, and a plurality of wires, wherein inner ends and outer ends of the wires are respectively connected to the inner ring and the outer ring, and the prefabricated lead frame has a wire shape corresponding to a chip and a substrate to be bonded. The prefabricated lead frame may be manufactured in batch production to increase the manufacturing efficiency of semiconductor devices, and the prefabricated lead frame may be used instead of a general wire bonding process.

Abstract: A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small.

Abstract: A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads, a first power lead arranged between the pair of first and second differential signal leads, a second power lead arranged between the pair of second and third differential signal leads, and a third power lead between which and the second power lead is the pair of third differential signal leads. A voltage provided by the first power lead is less than a voltage provided by the second power lead, and the voltage provided by the second power lead is substantially equal to a voltage provided by the third power lead.

Abstract: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.

Abstract: Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer.

Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.

Abstract: A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.