Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.

Abstract: A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test.

Abstract: A package for receiving electronic part has a heat radiating plate having a mounting area where the electronic part is mounted at a center portion of one main surface, a frame body adhered to the one main surface to surround the mounting area, and a wiring conductor derived from the inside to the outside of the frame body. The heat radiating plate has a metallic base body, a metallic body filling inside of the metallic base body, and a metal layer deposited on the metallic base body and the metallic body. The mounting area is formed on the metal layer so as to be located above the metallic body, both of the metallic body and the metal layer have higher thermal conductivity than the metallic body, and both of the frame body and the metallic base body have a smaller coefficient of thermal expansion than the metal layer.

Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract: Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups.

Abstract: A rectangular-shaped controlled collapse chip connection (C4) is described. In one embodiment, there is a semiconductor chip package that comprises a semiconductor chip package substrate and a semiconductor chip having a plurality of rectangular-shaped C4 contacts attached thereto that connect the semiconductor chip to the semiconductor chip package substrate. The plurality of rectangular-shaped C4 contacts are arranged along a surface of the semiconductor chip in an orientation that extends radially from a center of the surface of the semiconductor chip.

Abstract: A package includes an internal package stacked upon a primary die. The package includes interconnection balls to allow the package to be electrically and physically connected to a mother board. The package is mounted to the mother board in a single operation thus minimizing labor and the associated manufacturing cost. Further, the package is tested and verified to be non-defective prior to mounting to the mother board.

Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Abstract: The present invention is directed to improving the efficiency of removing heat from semiconductor devices. In addition, the method of manufacturing the improved devices has the potential of eliminating a key step in the traditional production process where the chips are highly susceptible to mechanical damage. A semiconductor element includes a semiconductor substrate having a heat removal side and a heat producing region, and at least one superstrate semiconductor layer defining the heat producing region. The heat removal side of the semiconductor substrate includes at least one recess region which extends closer to the heat-generating region than the remainder of the heat removal surface.

Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a fluorescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal structure and a second exposed metal structure. The metal feature is selectively formed on the first exposed metal structure without forming on the second exposed metal structure. By adjusting a concentration of stabilizer in an electroless plating solution, the metal feature is electrolessly plated on the first exposed metal structure without plating metal on the second exposed metal structure.

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract: A semiconductor film formed on a substrate is crystallized by continuously oscillating type laser. The scanning direction of the continuously oscillating type laser and the crystallization direction are coincident with each other. Adjustment of the crystallization direction and the charge transferring direction of the thin film transistors makes control of the characteristics of the thin film transistors possible. With respect to the laser treatment device for crystallizing the semiconductor film, the beam shape of laser oscillated from the continuously oscillating type laser device is made to be elliptical by a cylindrical lens and said cylindrical lens is made rotatable and said laser beam is scanned on said substrate by a galvanomirror and said laser beam can be focused upon said substrate by f-?lens.

Abstract: Check valve package for pb-free, single piece electronic modules, the package having an exterior and an interior, and at least one electronic device mounted within the interior of the package electrically connected to a lead-free solder ball grid array on a surface of the package, the package having a check valve between the interior and exterior of the package configured to allow flow from the interior to the exterior and to prevent flow form the exterior to the interior. The package withstands the solder reflow temperatures for the reflow of the pb-free solder balls of a ball grid array packaging of an NVSRAM during mounting on a circuit board. The package is suitable for packaging circuits containing rechargeable batteries and for packaging other electronic devices.

Abstract: A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

Abstract: A thermal treatment apparatus, a method for manufacturing a semiconductor device, and a method for manufacturing a substrate, wherein the occurrence of slip dislocation in a substrate during heat treatment is reduced, and a high-quality semiconductor device can be manufactured, are intended to be provided. A substrate support 30 is formed from a main body portion 56 and a supporting portion 58. In the main body portion 56, a plurality of placing portions 66 extend parallel, and supporting portions 58 are provided on the placing portions 66. A substrate 68 is placed on the supporting portion 58. The supporting portion 58 has a smaller area than an area of a flat face of the substrate, and is formed from a silicon plate having a thickness larger than thickness of the substrate, so that deformation during heat treatment is reduced. The supporting portion 58 is made of silicon, and a layer coated with silicon carbide (SiC) is formed on a substrate-placing face of the supporting portion 58.

Abstract: A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell.

Abstract: For the vertical electrical connection of a number of components, an electronic structure with at least two components has solderable connecting elements, which include at least one socket element and a solder ball stacked on the socket element. The socket element has a cylindrical core of an electrically conducting first material with a lateral surface, a bottom surface and a top surface. The core is surrounded with a cladding of an electrically insulating second material in such a way that the lateral surface of the core is covered by the cladding and the top surface and the bottom surface are kept free of the cladding.