Abstract: An LED backlight device includes a substrate having an optical transparency and an LED thin-film layered structure fixed to a first surface of the substrate. The LED thin-film layered structure is formed of epitaxially grown inorganic material layers as a P-N junction device. An anode electrode and a cathode electrode are formed on the LED thin-film layered structure. An anode driver IC and a cathode driver IC are provided for driving the LED thin-film layered structure. A wiring structure electrically connects the anode driver IC and the anode electrode of the LED thin-film layered structure and electrically connects the cathode driver IC and the cathode electrode of the LED thin-film layered structure. A phosphor is formed on the second surface of the substrate opposite to the first surface.

Abstract: A backlight device includes a first substrate, and an LED thin-film layered structure (epitaxially grown inorganic material layers) fixed to a surface of the first substrate. An anode electrode and a cathode electrode are formed on the LED thin-film layered structure. An anode driver IC and a cathode driver IC are provided for driving the LED thin-film layered structure. A wiring structure electrically connects the anode driver IC and the anode electrode of the LED thin-film layered structure, and electrically connects the cathode driver IC and the cathode electrode of the LED thin-film layered structure. A second substrate has an optical transparency and is disposed to face the surface of the first substrate on which the LED thin-film layered structure is formed. A phosphor is formed on a surface of the second substrate facing the first substrate and is disposed on a position corresponding to the LED thin-film layered structure.

Abstract: An LED backlight device includes a first substrate having optical transparency and having first and second surfaces. An LED thin-film layered structure is fixed to the first surface of the first substrate, and is formed of epitaxially grown inorganic material layers as a P-N junction device. An anode electrode of the LED thin-film layered structure is connected to an anode driver IC via an anode wiring. A cathode electrode of the LED thin-film layered structure is connected to a cathode driver IC via a cathode wiring. A phosphor is provided on the second surface of the first substrate. The LED backlight device further includes a second substrate having optical transparency and having first and second surfaces. The first surface of the second substrate faces the first surface of the first substrate. A reflection layer is provided on the second surface of the second substrate.

Abstract: A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active surface of the sensor die and separate from the imaging area.

Abstract: An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate; and forming a back-surface element aligned with respect to the element, on a back-surface side of the Si substrate after the substrate is etched. A mark is formed by etching and removing the Si layer and the insulating layer in a predetermined position of the SOI substrate. The element is formed using a concave part as a reference position. The concave part appears on the front surface of the Si substrate epitaxially grown on the mark. The back-surface element is formed using the mark as a reference position. The mark appears after the substrate is etched.

Abstract: A semiconductor device includes a film containing silicon as the main ingredient, and an aluminum alloy film, such as a source electrode and a drain electrode, that is directly connected to the film containing silicon as the main ingredient, such as an ohmic low-resistance Si film, and contains at least Al, Ni, and N in the vicinity of the bonding interface. The Aluminum alloy film has a good contact characteristic when directly connected to the film containing silicon as the main ingredient without having a barrier layer formed of high melting point metal.

Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.

Abstract: A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask. The core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the top surface; herein the interconnection portion includes a surface dielectric layer and a surface circuit layer disposed on the surface dielectric layer. The surface circuit layer is electrically connected to the circuit pattern. The solder mask is disposed on the interconnection portion; herein the solder mask includes a hole to identify the substrate structure. Besides, a method for manufacturing the substrate structure is disclosed.

Abstract: There is provided a semiconductor chip and a multi-chip package. Each semiconductor chip includes a plurality of pads formed on a first surface thereof and electrically connected to an integrated circuit, and interconnection patterns formed as stripes on a second surface of the semiconductor chip. The interconnection patterns are formed by transferring a part of the basic layout configured with a pattern of stripes extending from a center portion to an edge portion, wherein the pads are electrically connected to the interconnection patterns.

Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.

Abstract: A package of the present invention has a laminate structure formed by laminating a plurality of ceramic layers, and has a mount surface to be a joint surface when mounted on a mother board, defined parallel with the laminating direction. A first ceramic layer has a recess with an L-shaped cross section across the mount surface and a side surface, defined at each end thereof in a direction perpendicular to the laminating direction, and an external electrode formed on each recess, the external electrode having a surface thereof exposed to the mount surface.

Abstract: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection through hole is constructed to provide an electrical connection between the plating lead lines on the wire bonding pad side and the ball pad side, thereby preventing electrical disconnection when the plating lead line of the wire bonding pad side is cut.

Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.

Abstract: Disclosed are a metal interconnection of a semiconductor device and a method for manufacturing the same, capable of improving the reliability of the semiconductor device. The metal interconnection of the semiconductor device includes a first metal interconnection formed on a semiconductor substrate; an interlayer dielectric layer formed on the semiconductor substrate including the first metal interconnection, the interlayer dielectric layer being selectively removed to form a via hole and a trench on the via hole; a metal diffusion blocking layer formed in the via hole and the trench formed on the via hole; a second metal interconnection buried in the via hole and the trench below a top portion of the metal diffusion blocking layer; and a protection layer covering the interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.

Abstract: An integrated circuit die includes a substrate having a front surface and a back surface, wherein the substrate front surface has electrical circuits formed thereon, and the substrate back surface has a plurality of metal layers formed thereon. The plurality of metal layers comprises at least one layer having a thickness of greater than about ten micrometers. The outermost metal layer may be mechanically and thermally bonded to a package using a die attach layer comprising a thermally conductive reflowable material. The invention advantageously facilitates the dissipation of heat from the integrated circuit die.

Abstract: A transmissivity controlled film 12 (CrO or the like), a transmissivity reduced film 13 (Cr or the like), and a resist film 14, for instance, are sequentially formed on, e.g., a transparent substrate 11. A resist is removed from an area (an area C) where a light-transmission section is to be formed, and the transmissivity reduced film 13 and the transmissivity controlled film 12 are removed from the area, thereby forming a light-transmission section. Next, a resist is removed from an area (an area A) in which a graytone section is to be formed, thereby removing the transmissivity reduced film 13 from that area, to thereby form a graytone section. Thus, a graytone mask is manufactured.

Abstract: The invention provides a semiconductor light emitting device and the fabrication method of the same. The semiconductor light emitting device according to the invention comprises a multi-layer light emitting structure and a heat conducting layer. The multi-layer light emitting structure comprises a first layer. The first layer has an exposed first surface, and it also has a first thermal conductivity. The heat conducting layer is formed on and covers the first layer. The heat conducting layer has a second thermal conductivity, wherein the second thermal conductivity is greater than the first thermal conductivity.

Abstract: A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor imaging element. The upper surface of each cylindrical electrode and the upper surface of the transparent resin layer are substantially of the same height.

Abstract: A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

Abstract: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.