Abstract: A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.

Abstract: Generally, the present disclosure provides example embodiments relating to a package attached to a printed circuit board (PCB). In an embodiment, a structure includes a PCB. The PCB has ball pads arranged in a matrix. Outer ball pads are along one or more outer edges of the matrix, and each of the outer ball pads has a first solder-attach area. Inner ball pads are interior to the matrix, and each of the inner ball pads has a second solder-attach area. The first solder-attach area is larger than the second solder-attach area.

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

Abstract: An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

Abstract: Provided is a technique for preventing warps of cooling plates due to a contraction of a joining material, thereby preventing a reduction in cooling performance of a semiconductor device. The semiconductor device includes the following: a first cooling plate; a second cooling plate facing the first cooling plate; a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and a case containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip. The semiconductor chip is mounted in a semiconductor-chip mounting part between the first cooling plate and the second cooling plate. The case is provided with a portion corresponding to the semiconductor-chip mounting part and to surroundings thereof. The portion has an up-and-down width greater than an up-and-down width of the remaining portions of the case.

Abstract: A bonded body of the present invention includes a ceramic member formed of ceramics and a Cu member formed of Cu or a Cu alloy. In a bonded interface between the ceramic member and the Cu member, a Cu—Sn layer which is positioned on the ceramic member side and in which Sn forms a solid solution in Cu, a first intermetallic compound layer which is positioned on the Cu member side and contains Cu and Ti, and a second intermetallic compound layer which is positioned between the first intermetallic compound layer and the Cu—Sn layer and contains P and Ti are formed.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Abstract: A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.

Abstract: A method of forming contacts to an embedded semiconductor die includes embedding a semiconductor die in an encapsulation material, the semiconductor die having a first terminal at a first side of the semiconductor die, forming a first metal mask on a first surface of the encapsulation material, the first metal mask being positioned over the first side of the semiconductor die and exposing a first part of the encapsulation material aligned with the first terminal of the semiconductor die, directing a pressurized stream of liquid toward the first surface of the encapsulation material with the first metal mask, to remove the first exposed part of the encapsulation material and form a first contact opening to the first terminal of the semiconductor die, and forming an electrically conductive material in the first contact opening. Related semiconductor packages are also described.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.

Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

Abstract: A barrier film. The barrier film may include a substrate, an inorganic layer disposed on a side of the substrate, and an organic layer-by-layer structure disposed on a side of the inorganic layer, where in the organic layer-by-layer structure comprises a layer of a cationic polyelectrolyte and a layer of an anionic polyelectrolyte.

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.