Abstract: A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: An organic light emitting diode (OLED) device and the method of fabricating thereof. The OLED device includes a substrate, a display region, a non-display region, and an encapsulation structure covering the display region and the non-display region. The non-display region is composed of a flexible substrate that is bendable, the flexible substrate is curved toward a second surface of the substrate. The non-display region is provided with at least one groove structure at an edge adjacent to the display region, the groove structure extends along a first direction which is parallel to a boundary line between the display region and the non-display region.

Abstract: A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel.

Abstract: A method for forming a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

Abstract: Aspects of the present disclosure provide a method for fabricating a 3D semiconductor apparatus. The method can include forming a multilayer stack including a plurality of dielectric layers. The dielectric layers can include three or four dielectric materials that can be etched selectively with respect to one another. The method can also include forming opening(s) in the multilayer stack, and filling the opening(s) with first and second channel materials to form first and second channels that interface at a transition dielectric layer the multilayer stack. The method can also include removing second and first source/drain (S/D) dielectric layers of the multilayer stack and replacing with second and first S/D materials to form second and first S/D regions, respectively. The method can also include removing gate dielectric layers of the multilayer stack and replacing with a gate material to form gate regions of the 3D semiconductor apparatus.

Abstract: The present application discloses a semiconductor device with porous decoupling features and the method for fabricating the semiconductor device with the porous decoupling features. The semiconductor device comprises: a substrate; a first conductive line positioned on the substrate and extend along a first direction; a first conductive line spacer positioned on a sidewall of the first conductive line; a bottom contact positioned adjacent to the first conductive line; a bottom contact spacer positioned on a sidewall of the bottom contact; and a porous insulating layer positioned between the first conductive line spacer and the bottom contact spacer; wherein a porosity of the porous insulating layer is between about 25% and about 100%.

Abstract: A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.

Abstract: The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

Abstract: A display panel and a display device are provided. The display panel is divided into a display area, a transition area, and a bending area. The display panel includes a first recess and a second recess. The first recess is disposed in the bending area, and the second recess is disposed in the transition area.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Abstract: An image sensor includes a sensor region for receiving light and generating an image data and a pad region adjacent to the sensor region, an insulation layer on the substrate, and a lower transparent electrode on the insulation layer in the sensor region, and an etch stop layer on the insulation layer in the sensor region and pad region. The etch stop layer may include silicon nitride. A height of an uppermost surface of the lower transparent electrode may be substantially equal to a height of an upper surface of the etch stop layer, with respect to the substrate.

Abstract: The present disclosure provides a display assembly, a display device, and a manufacturing process. The display assembly includes: a substrate; a display element arranged in a display region of the substrate; a package film covering the display element; a driving circuit arranged in a non-display region of the substrate; a chip-on-film bonded with the driving circuit; and a support portion arranged in the non-display region of the substrate and outside the package film.

Abstract: A flexible substrate is provided. The flexible substrate includes a flexible base substrate made of a flexible material. The flexible base substrate has a plurality of gaps and a plurality of solid non-gap portions, at least two adjacent solid non-gap portions of the plurality of solid non-gap portions being interconnected. The flexible base substrate includes a strengthening layer in the plurality of solid non-gap portions, the strengthening layer including a strengthening material having a Young's modulus greater than a Young's modules of the flexible material.

Abstract: A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.