Abstract: Provided is a display device including: a base substrate; a light-emitting element provided on one surface side of the base substrate; and a sealing film provided covering the light-emitting element, wherein the sealing film includes a first inorganic film and a second inorganic film sequentially provided covering the light-emitting element, and a resin layer provided in an island shape between the first inorganic film and the second inorganic film.

Abstract: The present disclosure protects a flexible substrate and prevents the generation of a crack and the development of a crack inside a display device. A display device includes a display area and a frame region which is a non-display area provided outside the display area, and in the frame region, at least a flexible substrate and a moisture-proof layer are disposed in this order, and a metal oxide film is further provided between the flexible substrate and the moisture-proof layer.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

Abstract: A display device includes: a base substrate; a first pixel electrode, a second pixel electrode, and a third pixel electrode arranged on the base substrate to be spaced apart from each other; a pixel defining film on the first pixel electrode, the second pixel electrode, and the third pixel electrode and including a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode and spaced apart from the first opening, and a third opening exposing the third pixel electrode and spaced apart from the first opening and the second opening; a first organic layer on the first pixel electrode exposed by the first opening; a second organic layer on the second pixel electrode exposed by the second opening; and a third organic layer on the third pixel electrode exposed by the third opening.

Abstract: Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se.

Abstract: A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

Abstract: A display back panel may include a substrate, an insulating layer disposed on one side of the substrate and including a plurality of recesses, the plurality of recesses including a bottom surface, a first electrode disposed on a surface of the insulating layer away from the substrate, a pixel defining layer disposed on a surface of the first electrode away from the substrate and including a plurality of openings, a light-emitting layer disposed in the plurality of openings and covering the first electrode, and a second electrode disposed on a surface of the light-emitting layer away from the substrate. Therein, the first electrode may reflect waveguide light laterally propagated by the light-emitting layer, thereby improving a light-emitting efficiency of the light-emitting layer. Further, the reflected waveguide light may not be absorbed by the second electrode, thereby enhancing an external quantum effect of the light-emitting layer.

Abstract: A light-emitting device, a method of manufacturing the same and an electronic apparatus. The light-emitting device includes a silicon-based base substrate; at least one organic light-emitting diode device at the silicon-based base substrate; a first encapsulation layer, at a side of the at least one organic light-emitting diode device away from the silicon-based base substrate and including one or more sublayers; a color filter layer, at a side of the first encapsulation layer away from the at least one organic light-emitting diode device; and a second encapsulation layer, at a side of the color filter layer away from the first encapsulation layer and including one or more sublayers. A refractive index of at least one sublayer in the first encapsulation layer is greater than a refractive index of at least one sublayer in the second encapsulation layer.

Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.

Abstract: A display apparatus includes: a base substrate including a display area, an opening area, and an opening peripheral area between the opening area and the display area, wherein the display area surrounds the opening area, and the opening peripheral area has an annular shape; a conductive pattern disposed on the base substrate in the opening peripheral area and having an annular shape; and a light emitting layer disposed on the base substrate and in a portion of the opening peripheral area, and including an organic material, and wherein the light emitting layer is not formed at a portion of opening peripheral area that is adjacent to the opening area.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

Abstract: A display panel including a substrate, multiple display pixels, an encapsulation structure, and an auxiliary layer is provided. The substrate includes a display region, a bendable region, and a buffer region positioned therebetween. The display pixels are disposed in the display region. The encapsulation structure is overlapped with the display region and covers the display pixels. The auxiliary layer is overlapped with the bendable region and has a top surface. A first height is included between a top surface of the auxiliary layer and a surface of the substrate. The auxiliary layer and the encapsulation structure define a recess overlapped with the buffer region. A second height is included between a bottom surface of the recess positioned in the buffer region and the surface of the substrate. A difference between the first height and the second height is greater than 0 ?m and less than or equal to 4 ?m.

Abstract: A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel.

Abstract: The present disclosure provides a semiconductor device with a carbon liner over a gate structure and a method for forming the semiconductor device. The semiconductor device includes a gate structure disposed over a semiconductor substrate. The semiconductor device also includes a carbon liner covering a top surface and sidewalls of the gate structure and a top surface of the semiconductor substrate. The semiconductor device further includes a bit line contact disposed over the semiconductor substrate. The bit line contact extends over the gate structure, and the bit line contact is electrically separated from the gate structure by the carbon liner.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: The present disclosure relates to a solid-state image pickup device and an electronic apparatus that are capable of preventing leakage of charges between adjacent pixels. A plurality of pixels perform photoelectric conversion on light incident from a back surface via different on-chip lenses for each pixel. A pixel separation wall is formed between pixels adjacent to each other, and includes a front-side trench formed from a front surface and a backside trench formed from the back surface. A wiring layer is provided on the front surface. The present disclosure is applicable to, for example, a backside illuminated CMOS image sensor.

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

Abstract: Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.