Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: In one embodiment, a decompression circuit is provided for a data stream that includes code words representing compressed data and uncompressed data. The decompression circuit includes a translation circuit adapted to identify the code words in the data stream and to translate the identified code words into corresponding decompressed data words; and a shift register operable to serially shift in uncompressed data in the data stream and to shift in parallel the decompressed data words from the translation circuit.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: The invention relates to a device for digital-to-radio frequency conversion, the device comprising: conversion cell matrices for digital-to-radio frequency conversion; means for providing a digital data signal; means for dividing the digital data signal into data signal groups; means for generating clock signals, the clock signals having different phases, the number of clock signals being the same as the number of data signal groups; means for synchronizing the data signal groups by using the clock signals; means for conveying the synchronized data signal groups to the conversion cell matrices, the number of conversion cell matrices being the same as the number of data signal groups; and means for synchronizing each conversion cell matrix by using the clock signal with which the synchronized data signal group conveyed thereto was synchronized for generating interpolation values.

Abstract: In an information transmitting device, a variable capacitor which is charged to have a predetermined voltage discharges through a predetermined resistor. Until the voltage becomes lower than a predetermined threshold voltage, the number of AC signals having a predetermined frequency is counted. Accordingly, first continuous amount information of a binary code corresponding to a writing pressure is obtained and is converted to a Gray code, which is regarded as second continuous amount information. A resonant circuit is opened or shorted in accordance with ‘0’ or ‘1’ in the second continuous amount information, so as to transmit the second continuous amount information.

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: An asynchronous sampling arrangement utilizes sampling of both a high speed data signal and a trigger (clock) signal. The data signal may be either an optical signal or an electrical signal. The data and trigger signals are sampled in parallel by two separate gates, the gates based on the same strobe frequency. The samples corresponding to the trigger signal are then processed through an algorithm that determines the time-base related to the sampled signal. This established time-base is then used to reconstruct the sampled version of the high data rate input signal waveform.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.

Abstract: Described are techniques for performing lossy encoding. Source data and quality data are received by an encoder. The encoder maps the source data into a compressed representation having a level of distortion in accordance with the quality information. The compressed representation may be decoded without using the quality information.

Abstract: The present invention provides an adaptive, intelligent transform based Analog to Information Converter (AIC) for wideband signals by directly converting an analog signal to information (e.g., features, decisions). This direct conversion is achieved by (i) capturing most of the information of a wideband signal via hardware/software implemented mathematical transformations, (ii) effectively removing unwanted signals such as jammer and interfere from the input signal, and (iii) using novel algorithms for highly accurate decision making and feature extraction (e.g., high probability of detection with low probability of false alarm). The jump in the improvement over today's state-of-the-art is in terms of effective and optimum signal information extraction at high-speed.

Abstract: Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

Abstract: A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n?1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.

Abstract: A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: Character strings in sample data are classified into groups of character strings with the same leading n characters (for example, “abc”). Then, one character string with the highest appearance frequency (the most frequently appearing character string) in the sample data is extracted from each group. The most frequently appearing character strings extracted from each group are registered in a dictionary as initial values in descending order of appearance frequency. Alternatively, character strings in sample data are classified into groups of character strings with the same hash value of leading n characters, the most frequently appearing character string is detected from each of the groups and the most frequently appearing character string is registered in the dictionary as an initial value.

Abstract: Various embodiments of the present invention are directed to a binary signal converter that facilitates distinguishing an original direct signal on a nanowire by superimposing an alternating signal on the original direct signal. The binary signal converter includes an alternating signal source connected to the nanowire that superimposes an alternating signal with an initial amplitude on the nanowire. The binary signal converter may also include a selective alternating signal filter that selectively passes the alternating signal from the nanowire to a signal sink.

Abstract: To provide a decoding method and a decoding device capable of reducing a power consumption in a decoding processing and a program for the same. The decoding method to be executed by a decoding device decoding a data to be decoded including a header data and an encoded data, including a steps of: generating a prediction load data indicating a prediction load in a decoding processing for the encoded data, based on an attribute data of the encoded data included in the header data; determining an operating frequency based on the generated prediction load data; and operating at the determined operating frequency to decode the encoded data.

Abstract: An arithmetic decoding method and apparatus are provided. The apparatus includes an arithmetic decoding apparatus comprising an arithmetic decoding unit determining a range of a most probable symbol and a range of a least probable symbol required to decode a current symbol, comparing a current offset and the range of the most probable symbol required to decode the current symbol, and determining and outputting the value of the current symbol. The apparatus also includes a predicted arithmetic decoding unit determining a range of a most probable symbol and a range of a least probable symbol which are required to decode a next symbol using a prediction that the current symbol is the most probable symbol, comparing a next offset and the range of the most probable symbol required to decode the next symbol, and determining and outputting a range of the next symbol.

Abstract: A circuit has a first amplifier having first positive and negative inputs and a second amplifier having second positive and negative inputs. A first unit is connectable to the first and second inputs of the amplifiers and a second unit is connectable to the first and second inputs of the amplifiers. In a first phase, the first unit is connected to the amplifiers, wherein the positive input of the first amplifier is coupled to the positive input of the second amplifier and the negative input of the first amplifier is coupled to the negative input of the second amplifier. In a second phase, the second unit is connected to the amplifiers, wherein the positive input of the first amplifier is coupled to the negative input of the second amplifier and the negative input of the first amplifier is coupled to the positive input of the second amplifier.