Abstract: A method, apparatus and computer program for decoding a data stream. The method comprises the steps of acquiring an analog data signal, determining an initial polarity of the analog data signal, determining a threshold transition level, determining a plurality of transition edges where the analog data signal crosses the threshold transition level, and determining the number of unit intervals between each pair of transition edges. A binary value is assigned to each of the unit intervals, and the binary values are displayed to a user.

Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Abstract: An input analog signal is fed to an amplifier circuit and an AD converter circuit. The AD converter circuit converts the input analog signal into a digital value of a predetermined number of bits, and outputs the digital value to an encoder (not shown) A DA converter circuit converts the digital value of a predetermined number of bits output from the AD converter circuit into an analog signal. The amplifier circuit samples and amplifies the input analog signal by a factor of ? (greater than 1). A subtracter circuit subtracts an output of the DA converter circuit amplified by a factor of ? from an output of the amplifier circuit.

Abstract: A recording method for converting m-bit data into n-bit (where n>m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.

Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. The method generally comprises forming a first compressed sensing matrix utilizing a first set of time indices corresponding to a first sampling rate, forming a second compressed sensing matrix utilizing a plurality of frequencies and a second set of time indices corresponding to a second sampling rate, forming a combined compressed sensing matrix from the first compressed sensing matrix and the second compressed sensing matrix, and reconstructing at least a portion of the input signal utilizing the combined compressed sensing matrix. The first and second sampling rates are each less than the Nyquist sampling rate for the input signal.

Abstract: A method for compressing a frame-based program image (FBPI) includes identifying common envelope data in the FBPI. Identified common envelope data is removed from the FBPI. At least one instance of an identical repeated frame of the FBPI is identified. A first instance of an identified identical repeated frame is replaced with a pointer to a second instance of the identified identical repeated frame. A method for decompressing a compressed FBPI includes identifying at least one pointer in a compressed FBPI, wherein the at least one pointer comprises a reference to an identical repeated frame of the FBPI. The identified at least one pointer is replaced with the identical repeated frame to which the at least one pointer refers, to generate a half-decompressed FBPI. Envelope data is inserted into the half-decompressed FBPI to generate a full-decompressed FBPI. A computer program product and a system for compressing/decompressing an FBPI are also provided.

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract: Delta-sigma modulators with a selectable noise transfer function are described. In various embodiments, the noise transfer function is varied in accordance with a bandwidth, a communication protocol, or an oversampling ratio of a selected communication channel.

Abstract: A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at least one second clocked-operation accumulator stage connected in series with the first accumulator stage, with its input side coupled to an accumulator output of the first accumulator stage. The sigma-delta converter is configured to process the data word upon each clock signal only in one accumulator stage in the first and the at least one second accumulator stage, and output the processed data word at the accumulator output of the one accumulator stage. As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.

Abstract: A voice signal is transmitted in an MOST network on a single channel. The width of the transmitted voice data words is preferably up to 14 bits, and each voice data word is transmitted into successive clock periods of the MOST network, in a byte that includes seven bits of the voice data word and one identifier bit.

Abstract: Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analog signal by a digital/analog converter, the conversion clock being varied according to the frequency hopping method.

Abstract: A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

Abstract: A video signal processing apparatus comprises an A/D converter for digitizing an analog video signal, an integration circuit for integrating the digitized video signal within a predetermined integration range, a picture display device for displaying a picture based on an integration output, and a control unit which, when an offset adjustment signal is inputted to the A/D converter, corrects the offset value so as to eliminate a difference between the integration value of the integration circuit and a preliminarily set specified value, and determines whether or not offset adjustment is completed based on the number of times when the corrected offset value is within a range defined by adding a predetermined error to the specified value.

Abstract: Entropy encoders and decoders employ an entropy-pump operation. The entropy-pump operation includes classifying blocks of the input sequence's symbols in accordance with the probabilities of occurrence of those blocks' values. Entropy coding an output component that represents the sequence of classes to which the blocks belong tends to be profitable, because that component has an entropy density less than that of the input sequence. In contrast, little opportunity for compression tends to be lost by not entropy encoding an output component that represents the values of the blocks that belong to single class, because those values' probabilities of occurrence are similar.

Abstract: A variable-length encode/decode processor includes a central processing unit and an instruction buffer and a getbits processing engine coupled to the central processing unit. Such a processor can be used to encode data as variable-length symbols or to decode variable-length symbols such as those found in an MPEG bitstream.

Abstract: The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link. This device allows detection of laser beam to work surface misalignment and the termination of lasing before critical active circuit components can be damaged.

Abstract: A sigma-delta modulator is provided with a filter for noise shaping, with the filter having at least one delay line (DL). The delay line (DL) is a clocked line.

Abstract: A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.

Abstract: The present invention provides an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.

Abstract: An improved clocked data converter with a vibrating microelectromechanical systems (MEMS) resonator. The MEMS resonator is used as part of the clock circuitry of an analog to digital converter or a digital to analog converter. The MEMS resonator may be used as the frequency determining element of an on-chip oscillator, or as a bandpass filter used to clean up an external clock signal.