Abstract: Disclosed is a bit-detection arrangement able to convert an analog signal (AS) having an amplitude into a digital signal (DS) representing a bit sequence from which the analog signal (AS) is derived. The bit-detection arrangement has a phase detector which detect the phase difference between a quantized analog signal and a clock signal C2. The phase difference is sampled by an AD converter. The AD converter can sample at a relatively slow rate as the phase difference is a low frequency signal. The sampled phase difference is fed to a digital PLL which outputs a phase signal PHI. The phase signal and the quantized analog signal are used to recreate the digital signal (DS).

Abstract: A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.

Abstract: A compensation method for a receiver is disclosed, the method includes: receiving and processing an incoming signal to generate an analog input signal; utilizing a time-interleaved parallel analog-to-digital converter (ADC) for converting the analog input signal to a digital input signal according to a plurality of clock signals of different phases; equalizing the digital input signal to generate a plurality of soft decision values; generating a plurality of hard decision values according to the soft decision values; calculating a plurality of error values according to the hard decision values and the soft decision values; and compensating the receiver according to at least part of the error values.

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).

Abstract: The present invention provides a digital signal processing apparatus which can perform batch processing of mixing and gain controlling, etc., one time while the frequency characteristics of different filters are being mixed to a plurality of input signals in case of the re-quantization only once.

Abstract: The present invention aims to realize linking of 1-bit signals having respective sampling frequencies that are different from each other and show a relationship of one equal to integer times of the other without noises.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output time stamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: A gain calibration system for an amplifier includes an amplifier having inputs and outputs and an analog to digital converter having inputs and an output. There is a voltage supply for providing a plurality of output voltages. A first switching circuit couples at least one of the output voltages to the inputs of the amplifier in a first phase. A second switching circuit couples the outputs of the amplifier to the inputs of the analog to digital converter in the first phase and couples the sum of all of the at least one output voltages to the input of the analog to digital converter in a second phase. A processor responsive to the outputs of the analog to digital converter in the first and second phases calculates a calibration factor to accommodate for amplifier gain error.

Abstract: A character string processing apparatus converting a character string encoded by a first encoding method to a second encoding method selected from a plurality of encoding methods is disclosed. The character string processing apparatus includes an encoding method determination part that selects the encoding methods, obtains, with respect to each selected encoding method, at least one of the number information and the position information of one or more replacement codes at the time of converting the character string to the selected encoding method, and determines the second encoding method based on at least one of the number information and the position information.

Abstract: A method for sampling audio data is provided. In this method, the audio data is received and sampled at a first sampling rate using a first interpolation calculation. Thereafter, the audio data sampled at the first sampling rate is again sampled at a second sampling rate using a second interpolation calculation. After sampling, the second audio data sampled at the second sampling rate is outputted. Circuitries and systems for sampling audio data also are described.

Abstract: The invention concerns a digital data compression encoder, characterized in that it comprises: an input for a first data flow (SH), and a second data flow (SL), an encoding module, matching symbols of the first data flow, and code words, wherein, for certain symbols, there exist several words, called redundant, corresponding to the same symbol, and a processing module for encoding the symbols of the first data flow based on the correspondence, by selecting among the redundant words, on the basis of at least part of the second data flow.

Abstract: In one set of embodiments, a temperature measurement system may include an analog to digital converter (ADC) to produce digital temperature readings according to a difference base-emitter voltage (?VBE) developed across a PN-junction. A clock generating circuit may be configured to provide a sampling clock used by the ADC, which in some embodiments may be a delta-sigma ADC, in performing the conversions. The clock generating circuit may be configured to change the frequency of the sampling clock a specified number of times within each one of the one or more conversion cycles to reduce an error component in the temperature measurement, where the error component is produced by an interfering signal, such as an electromagnetic interference (EMI) signal being coherent with the sampling clock, and/or a noise residing on the voltage supply and also being coherent with the sampling clock.

Abstract: A method of matching input amplitudes in a system wherein one or more of a plurality of inputs may be selected, with each input capable of having different characteristics, involving selecting an input signal and mapping the input signal to a predetermined signal amplitude through the use of level matching logic. The level matching logic may include a gain cell for increasing or decreasing the amplitude of the input signal.

Abstract: A delta sigma modulator look-ahead IIR filter response can be divided into a natural response and a pattern response using superposition techniques. The look-ahead delta sigma modulators of the signal processing systems described herein include an infinite impulse response filter (“IIR”) that produces multiple output look-ahead natural responses to input signals having a look-ahead depth of “M”. The multiple output lookahead IIR filter reduces the amount of processing and memory used by the delta sigma modulator to generate quantizer output values. The multiple output lookahead IIR filter uses extended delay stages and modified feedback coefficients to concurrently produce multiple look-ahead natural responses. In one embodiment, the multiple output lookahead IIR filter concurrently produces M look-ahead natural responses.

Abstract: A data compression apparatus includes: a difference creating section that determines a difference between adjacent numerical values on continuity of numerical values constituting the data to be compressed so as to create new data to be compressed; an offset section wherein numerical values constituting the new data to be compressed consisting of the continued numerical values, which is created by the difference creating section, is subjected to an offset by a predetermined value; a divisional section that divides every numerical value of the data to be compressed, which is subjected to the offset by the offset section, into an upper significant digit bit portion and a lower significant digit bit portion; an upper significant data compression section that applies reversal compression processing to the upper significant digit data; and a lower significant data compression section that applies reversal compression processing to the lower significant digit data.

Abstract: Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.

Abstract: An apparatus for auto calibration of a display device, the apparatus including a signal generating unit for generating predetermined digital patterns, converting the digital patterns into R, G, B and Y, U, V color signals, converting the color signals into analog pattern signals, and outputting the analog pattern signals; a calibration performing unit for converting the analog pattern signals into digital pattern signals, adjusting the offset and gain of the digital pattern signals using control signals, and outputting the offset and gain of the digital pattern signals; and a control unit for operating the signal generating unit and the calibration performing unit once a calibration performing mode starts, comparing the digital pattern signals to reference values, and outputting the control signals for adjusting the offset and gain of the digital pattern signals such that the digital pattern signals are identical to the reference values.

Abstract: A Low-Cost Absolute Linear Optical Encoder (“LALOE”) for determining the absolute position of a read-head within the LALOE relative to a codestrip is disclosed. The LALOE may include an emitter module within the read-head, the emitter module having a plurality of light sources arranged in an light source pattern and a 90° Out-Of-Phase light source; and a detector module within the read-head, the detector module having a plurality of photo-detectors arranged in a photo-detector pattern corresponding to the light source pattern and a 90° Out-Of-Phase photo-detector corresponding to the 90° Out-Of-Phase light source.

Abstract: Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.

Abstract: In an information transmitting device, a variable capacitor which is charged to have a predetermined voltage discharges through a predetermined resistor. Until the voltage becomes lower than a predetermined threshold voltage, the number of AC signals having a predetermined frequency is counted. Accordingly, first continuous amount information of a binary code corresponding to a writing pressure is obtained and is converted to a Gray code, which is regarded as second continuous amount information. A resonant circuit is opened or shorted in accordance with ‘0’ or ‘1’ in the second continuous amount information, so as to transmit the second continuous amount information.