Patents Examined by Howard Weiss
  • Patent number: 9431574
    Abstract: A light-emitting device includes a pixel having a transistor provided over a substrate, and a light-emitting element. The transistor includes a single-crystal semiconductor layer which forms a channel formation region, a silicon oxide layer is provided between the substrate and the single-crystal semiconductor layer, a source or a drain of the transistor is electrically connected to an electrode of the light-emitting element, and the transistor is operated in a saturation region when the light-emitting element emits light. Further, in the light-emitting device, a gray scale of the light-emitting element is displayed by changing a potential applied to the gate of the transistor.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: August 30, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9421628
    Abstract: A method of manufacturing a printed circuit board includes: supplying solder paste so as to be offset from an electrode pad of a printed wiring board; flowing the solder paste during melting; and forming a region that is not covered with solder resist on the outer peripheral region adjacent to the electrode pad of the printed wiring board to which solder paste is supplied, thereby increasing a gap between a semiconductor package and the printed wiring board to prevent separation of the solder.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 23, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Satoru Higuchi
  • Patent number: 9419014
    Abstract: An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: August 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Girishankar Gurumurthy
  • Patent number: 9412605
    Abstract: Embodiments of the present disclosure relate generally to a method of passivating and/or removing oxides on a semiconductor surface by using ammonium sulfide, the ammonium sulfide is formed by reacting ammonia and hydrogen sulfide in a semiconductor processing chamber, therefore the ammonium sulfide can be used to clean and remove oxides on a semiconductor surface without the concern of ESH and storage, the ammonium sulfide can also be used to passivate a semiconductor surface by forming a layer of sulfur, and thus preventing the reformation of native oxides, the layer of sulfur can be optionally removed to reduce the thickness of the semiconductor material.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki
  • Patent number: 9412733
    Abstract: Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: August 9, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Yeeheng Lee
  • Patent number: 9412709
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 9, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheila F. Chopin, Min Ding, Varughese Mathew, Scott S. Roth
  • Patent number: 9406789
    Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: August 2, 2016
    Assignees: NEW YORK UNIVERSITY, THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Jerome Alexandre Bürki, Charles Allen Stafford, Daniel L. Stein
  • Patent number: 9406832
    Abstract: A waveguide-coupled MSM-type photodiode of the present invention comprises a structure in which a semiconductor light-absorbing layer and an optical waveguide core layer are adjacent and optically coupled to each other, has formed metal-semiconductor-metal (MSM) junctions which are arranged at an interval on the semiconductor light-absorbing layer, and is characterized in that of the MSM electrodes arranged at the interval, a voltage is set so that a reverse bias is applied to those MSM electrodes that are arranged on a light incidence side.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 2, 2016
    Assignee: NEC CORPORATION
    Inventors: Junichi Fujikata, Takahiro Nakamura
  • Patent number: 9406811
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
  • Patent number: 9401331
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 26, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 9401399
    Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Franz Hirler
  • Patent number: 9397120
    Abstract: An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first and second data line pairs separated by cutting portions and a plurality of active patterns electrically connected to the first and second data line pairs. The data lines extend in a second direction crossing the first direction. The active patterns overlap the cutting portion and overlap a first gate line.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Ha Hwang, Woong-Kwon Kim, In-Woo Kim, Seong-Young Lee, Kweon-Sam Hong, Dong-Hyun Yoo, Beom-Hee Han
  • Patent number: 9391023
    Abstract: A method for producing a metal contact in a semiconductor device is disclosed. The method comprises depositing a catalyst layer in a via hole, forming a catalyst from the deposited catalyst layer, and growing a carbon nanotube structure above the catalyst in the via hole. The method further comprises forming salicide from the catalyst, applying a chemical mechanical polishing (CMP) process to the carbon nanotube structure to remove top layers of catalyst and nanotube material, and depositing metal material above the carbon nanotube structure. Growing a carbon nanotube structure comprises absorbing a precursor on a surface of the catalyst formed in the via hole, forming a metal-carbon alloy from the catalyst and the precursor, and growing a carbon nanotube structure vertically from the via bottom. The carbon nanotube structure comprises a plurality of carbon nanotubes wherein the diameters of the carbon nanotubes are limited by the catalyst size.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, Ching-Fu Yeh, Chih-Wei Chang
  • Patent number: 9379185
    Abstract: A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Murshed M. Chowdhury, Brian J. Greene, Arvind Kumar
  • Patent number: 9379020
    Abstract: A method of selective formation of silicide on a semiconductor wafer, wherein the metal layer is deposited over the entire wafer prior to application of the SiProt mask such that any etching of the mask does not cause any surface deterioration of the silicon wafer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 28, 2016
    Assignee: NXP B.V.
    Inventors: Eric Gerritsen, Veronique De-Jonghe, Srdjan Kordic
  • Patent number: 9379115
    Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhyun Shin, Minchul Kim, Seong Soon Cho, Seungwook Chol
  • Patent number: 9379028
    Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Cai, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 9379193
    Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 28, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Roger M. Arbuthnot, Peter Moens
  • Patent number: 9373663
    Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai
  • Patent number: 9373655
    Abstract: An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 21, 2016
    Assignee: Sony Corporation
    Inventors: Tsutomu Imoto, Keiji Mabuchi