Patents Examined by Howard Weiss
  • Patent number: 9196562
    Abstract: A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (?m), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dirk Siepe, Reinhold Bayerer
  • Patent number: 9196822
    Abstract: A magnetoresistive effect element in one or more embodiments of the present invention is provided with a memory layer with a variable magnetization direction having a magnetic anisotropy in a direction perpendicular to a film surface, a reference layer with an invariable magnetization direction having the magnetic anisotropy in a direction perpendicular to the film surface, and a tunnel barrier layer formed between the memory layer and the reference layer. The tunnel barrier layer has a first portion at the central part in the film surface and a second portion at a peripheral part. The second portion contains at least boron and oxygen.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeto Fukatsu, Tatsuya Kishi, Masahiko Nakayama, Akiyuki Murayama
  • Patent number: 9190364
    Abstract: A die according to an embodiment includes a contact pad configured to provide an electrical contact to a circuit element included in the die, a lateral edge closest to the contact pad and a cover layer including a protective structure, the protective structure including at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad to couple the contact pad electrically to an external contact, wherein the protective structure is arranged between the lateral edge and the contact pad. Using an embodiment may reduce a danger of contamination of a top side of a die during fabrication and packaging a chip.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 17, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Bernhard Knuepfer
  • Patent number: 9182475
    Abstract: Provided is a sound source signal filtering method and apparatus. The sound source signal filtering method includes: generating two or more microphone output signals by combining sound source signals input through a plurality of microphones; calculating distances between the microphones and a sound source from which the sound source signals are emitted by using distance relationships according to frequencies of the sound source signals extracted from the generated microphone output signals; and filtering the sound source signals to obtain one or more sound source signals corresponding to a predetermined distance by using the calculated distances. Accordingly, it is possible to obtain only sound source signals emitted from a sound source at a particular distance from the microphone array among a plurality of sound source signals input through the microphone array.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hoon Jeong, Kwang-cheol Oh, Kyu-hong Kim, So-young Jeong
  • Patent number: 9180015
    Abstract: Methods and devices for correcting wear pattern defects in joints. The methods and devices described herein allow for the restoration of correcting abnormal biomechanical loading conditions in a joint brought on by wear pattern defects, and also can, in embodiments, permit correction of proper kinematic movement.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 10, 2015
    Assignee: ConforMIS, Inc.
    Inventors: Wolfgang Fitz, Raymond Bojarski, Philipp Lang
  • Patent number: 9182641
    Abstract: The signal line structure is disposed between a gate driver and a display area of a display. The signal line structure includes a substrate, first metal layers, a first insulation layer, second metal layers, a second insulation layer and third metal layers. The first metal layers are arranged in parallel and toward a first direction in the substrate. The first insulation layer is disposed in the substrate and covers the first metal layers. The second metal layers are disposed on the positions of the first insulation layer corresponding to the first metal layers. The second insulation layer is disposed on the second metal layers and the first insulation layer. The third metal layers are disposed on the positions corresponding to the second metal layers in the second insulation layer. The distance between two adjacent second metal layers is less than that between two adjacent first metal layers.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: November 10, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Chou Lan, Sung-Hui Huang, Chia-Chun Yeh, Ted-Hong Shinn
  • Patent number: 9171892
    Abstract: A organic light emitting display device includes a thin film transistor (TFT) having a gate electrode, a source electrode and a drain electrode which are insulated from the gate electrode, and a semiconductor layer which is insulated from the gate electrode and which contacts each of the source electrode and the drain electrode; and a pixel electrode electrically connected to one of the source electrode and the drain electrode. The gate electrode is made up of a first conductive layer and a second conductive layer on the first conductive layer, and the pixel electrode is formed of the same material as the first conductive layer of the gate electrode on a same layer as the first conductive layer of the gate electrode.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: October 27, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do-Hyun Kwon, Il-Jeong Lee, Choong-Youl Im, Dae-Hyun No, Jong-Mo Yeo, Cheol-Ho Yu
  • Patent number: 9159725
    Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 13, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hassan P. Forghani-Zadeh, Sameer Pendharkar
  • Patent number: 9153772
    Abstract: A device for increasing the magnetic flux density includes a semiconductor body and a first magnetic sensor integrated into the semiconductor body, whereby a housing section, which forms a cavity, is arranged above the sensor on the semiconductor surface and the cavity is filled with a ferromagnetic material and the material comprises a liquid.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 6, 2015
    Assignee: Micronas GmbH
    Inventor: Joerg Franke
  • Patent number: 9152923
    Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: October 6, 2015
    Assignee: D-Wave Systems Inc.
    Inventors: Richard G. Harris, Andrew J. Berkley, Jan Johansson, Mark Johnson, Mohammad Amin, Paul I. Bunyk
  • Patent number: 9150408
    Abstract: A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched to remove wafer material from areas defined by the second cavities. The mask is removed and etching then removes wafer material except as prevented by the hard mask layer. This leaves the first cavities with a first depth and further deepens the second cavities to a depth greater than the first depth. By suitably configuring the second cavities, a capped die can be formed by securing the wafer to a second wafer and removing at least a portion of the unsecured side of the first wafer to expose the second cavities, thereby forming a plurality of caps on the second wafer.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: October 6, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Li Chen, Mitul Dalal
  • Patent number: 9136144
    Abstract: A semiconductor wafer contains first semiconductor die. TSVs are formed through the semiconductor wafer. Second semiconductor die are mounted to a first surface of the semiconductor wafer. A first tape is applied to on a second surface of the semiconductor wafer. A protective material is formed over the second die and first surface of the wafer. The protective material can be encapsulant or polyvinyl alcohol and water. The wafer is singulated between the second die into individual die-to-wafer packages each containing the second die stacked on the first die. The protective material protects the wafer during singulation. The die-to-wafer package can be mounted to a substrate. A build-up interconnect structure can be formed over the die-to-wafer package. The protective material can be removed. Underfill material can be deposited beneath the first and second die. An encapsulant is deposited over the die-to-wafer package.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 15, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaegKi Lim, JaEun Yun, SungYoon Lee
  • Patent number: 9136504
    Abstract: An organic electroluminescent device comprising: a transparent substrate; a first electrode disposed over the substrate for injecting charge of a first polarity; a second electrode disposed over the first electrode for injecting charge of a second polarity opposite to said first polarity; an organic light-emitting layer disposed between the first and the second electrode, wherein the second electrode is reflective, the first electrode is transparent or semi-transparent, and one or more intermediate layers of dielectric material with a refractive index greater than 1.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: September 15, 2015
    Assignee: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED
    Inventors: Euan C. Smith, Faisal Qureshi, Jan Jongman
  • Patent number: 9130006
    Abstract: A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: September 8, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9131294
    Abstract: An apparatus includes first and second microphone arrangements, arranged to output first and second signals respectively and is operable in a first mode and a second mode. In the first mode, an output signal is generated based on the second signal and a third signal, where the second signal and, optionally, the first signal, can be used to compensate for ambient noise, for example, for noise cancellation when a telephone call is relayed through a speaker. In the second mode, an output signal is generated based on the first and second signals. In this manner, the combination of the first and second microphone arrangements provides a directional sensitivity that can pick up sound from a remote source, for example, in an audio or video recording session. The apparatus may include a sensor to allow automatic switching between one or more of modes, directional sensitivity patterns and types of recording session.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 8, 2015
    Assignee: Nokia Technologies Oy
    Inventor: Andrew P. Bright
  • Patent number: 9123906
    Abstract: An organic electroluminescence device is provided. The device comprises an anode base layer (110), a hole injection layer (120) on the anode base layer (110), a light emitting layer (130) on the hole injection layer (120), and a cathode electrode layer (140) on the light emitting layer (130). The material of the hole injection layer (120) is metal oxide or thiophene type compound. The hole injection layer (120) has advantages of improving the recombination probability of electron-hole and not being easily oxidized, so that the efficiency of the organic electroluminescence device is increased and the service life is prolonged. A method for manufacturing the organic electroluminescence device is also provided.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 1, 2015
    Assignee: OCEAN'S KING LIGHTING SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Mingjie Zhou, Ping Wang, Hui Huang, Xiaoming Feng
  • Patent number: 9117841
    Abstract: A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 25, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhihong Zhang, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 9111937
    Abstract: Semiconductor devices with multilayer flex interconnect structures. In some embodiments, a semiconductor device may include a semiconductor chip coupled to a planar substrate and a multilayer flex interconnect structure coupled to the semiconductor chip, the multilayer flex interconnect structure including at least: a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first and second conductive layers. The semiconductor device may also include another semiconductor chip coupled to the planar substrate and placed in a side-by-side configuration with respect to the semiconductor chip, where the multilayer flex interconnect structure provides electrical connections between at least two terminals of the semiconductor chip and at least two terminals of the other semiconductor chip.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: August 18, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Burton J. Carpenter, Jr., Twila J. Eichman
  • Patent number: 9105810
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting unit, a second semiconductor layer, a reflecting electrode, an oxide layer and a nitrogen-containing layer. The first semiconductor layer is of a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and is of a second conductivity type. The reflecting electrode is provided on the second semiconductor layer and includes Ag. The oxide layer is provided on the reflecting electrode. The oxide layer is insulative and has a first opening. The nitrogen-containing layer is provided on the oxide layer. The nitrogen-containing layer is insulative and has a second opening communicating with the first opening.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Ito, Hiroshi Katsuno, Shinya Nunoue
  • Patent number: 9099581
    Abstract: A photonic integrated circuit (I/C) includes a focusing sidewall or in-plane surface that redirects and focuses light from a waveguide to a photodetector structure. The focusing includes redirecting an optical signal to a width smaller than a width of the waveguide. The focusing of the light allows the photodetector structure to be outside a waveguide defined by parallel oxide structures. With the photodetector structure outside the waveguide, the contacts can be placed closer together, which reduces contact resistance.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Yun-Chung Neil Na, Yuval Saado, Yimin Kang