Patents Examined by Howard Weiss
  • Patent number: 9312372
    Abstract: A semiconductor device in which an element region including at least an IGBT region is formed on a semiconductor substrate is presented. The IGBT region including: a collector layer; a drift layer; a body layer; a gate electrode placed inside a trench extending from the front surface of the semiconductor substrate to the drift layer; an emitter layer; and a contact layer having a higher impurity concentration than the body layer. In the semiconductor device, assuming that an x direction is a direction in which the trench extends along the front surface of the semiconductor substrate and that a y direction is a direction orthogonal to the x direction along the front surface of the semiconductor substrate, a distance from the contact layer to the emitter layer in the x direction is larger than a distance from the contact layer to the trench in the y direction.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: April 12, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keisuke Kimura, Satoru Kameyama
  • Patent number: 9312221
    Abstract: A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 9312225
    Abstract: A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Kuo-Ching Hsu, Chen-Shien Chen, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 9299671
    Abstract: A MEMS device includes a MEMS substrate with a movable element. Further included is a CMOS substrate with a cavity, the MEMS substrate disposed on top of the CMOS substrate. Additionally, a back cavity is connected to the CMOS substrate, the back cavity being formed at least partially by the cavity in the CMOS substrate and the movable element being acoustically coupled to the back cavity.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 29, 2016
    Assignee: INVENSENSE, INC.
    Inventors: Fang Liu, Michael Julian Daneman, Brian Kim, Anthony Minervini
  • Patent number: 9299917
    Abstract: A magnetic tunnel junction (MTJ) device is provided that includes a MTJ element and a control wire. The MTJ element includes a top ferromagnet layer formed of a first magnetic material, a tunneling layer, and a bottom ferromagnet layer formed of a second magnetic material. The tunneling layer is mounted between the top ferromagnet layer and the bottom ferromagnet layer. The control wire is configured to conduct a charge pulse. A direction of charge flow in the control wire extends substantially perpendicular to a magnetization direction of the top ferromagnet layer. The control wire is positioned sufficiently close to the top ferromagnet layer to reverse the magnetization direction of the top ferromagnet layer when the charge pulse flows therethrough while not reversing the magnetization direction of the bottom ferromagnet layer when the charge pulse flows therethrough.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 29, 2016
    Assignee: Northwestern University
    Inventors: Joseph Shimon Friedman, Alan V. Sahakian
  • Patent number: 9293529
    Abstract: A semiconductor device includes a silicon substrate layer with a decoupling region. The decoupling region of the silicon substrate layer comprises an array of lamellas laterally spaced apart from each other by cavities. Each lamella of the array of lamellas comprises at least 20% silicon dioxide.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: March 22, 2016
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Thoralf Kautzsch
  • Patent number: 9293375
    Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin S. Petrarca, Stuart A. Sieg, Theodorus E. Standaert
  • Patent number: 9293468
    Abstract: A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Kun Park, Young-Jun Kwon
  • Patent number: 9291513
    Abstract: Provided is a strain sensing device using reduced graphene oxide (R-GO). The strain sensing device includes a flexible substrate, a gate electrode formed on the flexible substrate, a gate insulating layer configured to cover the gate electrode and include a part formed of a flexible material, an active layer formed of R-GO for sensing a strain, on the gate insulating layer, and a source and drain electrode formed on the active layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 22, 2016
    Assignee: INTELLECTUAL DISCOVERY CO., LTD.
    Inventors: Nae Eung Lee, Quang Trung Tran, Do Il Kim
  • Patent number: 9293362
    Abstract: This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Dong-Seok Kim, Seung-Bum Kim, Sei-Jin Kim
  • Patent number: 9293472
    Abstract: An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 22, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He Huang, Zhongshan Hong
  • Patent number: 9281387
    Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 8, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9276140
    Abstract: An imager module having an interposer chip electrically connected to and routing signals between an image sensor, a printed circuit board (PCB), and a voice coil motor (VCM) is disclosed. In some example embodiments, one or more surface mount devices (SMDs) may further be attached to the interposer chip, the PCB, or both the interposer chip and the PCB. The interposer chip may further have a cavity therethrough to allow light to impinge in the image sensor. The interposer chip may still further have through silicon vias (TSVs) to route signals from the PCB to the VCM.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: March 1, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Samuel Waising Tam
  • Patent number: 9263577
    Abstract: A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 9263351
    Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: February 16, 2016
    Assignee: Fudan University
    Inventors: Pengfei Wang, Qingqing Sun, Wei Zhang
  • Patent number: 9263455
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Patent number: 9255000
    Abstract: A semiconductor device includes a substrate, a first dielectric layer located above the substrate, a moving-gate transducer, and a proof mass. The moving-gate transducer is at least partially formed within the substrate and is at least partially formed within the first dielectric layer. The proof mass includes a portion of the first dielectric layer and a portion of a silicon layer. The silicon layer is located above the first dielectric layer.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 9, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Ando Lars Feyh, Po-Jui Chen, Markus Ulm
  • Patent number: 9257431
    Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Ravasio, Samuele Sciarrillo, Andrea Gotti
  • Patent number: 9257427
    Abstract: According to a structure herein, parallel fins comprise channel regions and source and drain regions. Parallel gate conductors are over and intersecting the channel regions of the fins. Electrical insulator material surrounds sides of the gate conductors. Each of the fins has a main fin body and wider regions extending from the main fin body between the electrical insulator material surrounding the sides of the gate conductors. The wider regions comprise a first wider region extending a first width from the main fin body and a second wider region extending a second width from the main fin body. The material of the second wider region is continuous between adjacent fins.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9249010
    Abstract: A lead frame packaged electronic chip. The packaged electronic chip includes a MEMS device, an integrated circuit and a wire bond electrically coupling the MEMS device and the integrated circuit. The packaged electronic chip is encased in a molding material. The packaged electronic chip further includes a mechanism that shields the wire bond and the input/output pads that couple the MEMS device and the integrated circuit from electromagnetic and radio frequency interference.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 2, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Carl James Raleigh, Brian William Cousins