Patents Examined by Howard Weiss
  • Patent number: 9247332
    Abstract: Systems and methods are disclosed for capturing sound for communication by mounting one or more intra-oral microphones to capture sound; and mounting a mouth wearable communicator in the oral cavity to communicate sound with a remote unit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: January 26, 2016
    Assignee: Sonitus Medical, Inc.
    Inventors: Reza Kassayan, John Spiridigliozzi
  • Patent number: 9246355
    Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, Stephen L. Colino
  • Patent number: 9236341
    Abstract: A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: January 12, 2016
    Assignee: XILINIX, INC.
    Inventors: Dong W. Kim, Myung-June Lee, Suresh Ramalingam
  • Patent number: 9233832
    Abstract: Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Anthony K. Stamper
  • Patent number: 9232908
    Abstract: According to a Magnetic Resonance Imaging (MRI) apparatus, a scanning-parameter limit calculating unit creates examination information that represents scanning conditions for collection of magnetic resonance signal data based on scanning parameters set by an operator; a scanning-condition edit/scan positioning unit creates a time chart that indicates the type and a sequential execution order of an event to be executed when collecting magnetic resonance signal data based on the examination information created by the scanning-parameter limit calculating unit, and causes a time-chart display unit to display the created time chart.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 12, 2016
    Assignees: TOSHIBA MEDICAL SYSTEMS CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi Sugiura
  • Patent number: 9236312
    Abstract: Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hong Yu, Hyucksoo Yang, Richard J. Carter
  • Patent number: 9236480
    Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: January 12, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9236453
    Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Grant
    Filed: March 30, 2014
    Date of Patent: January 12, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Patent number: 9236250
    Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
  • Patent number: 9230917
    Abstract: A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 5, 2016
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Tarja Hauck, Alessia Sciré, Dieter Kaiser, Andreas Greiner, Morgana Nicolo, Carolin Wetzig, Dietrich Burmeister
  • Patent number: 9231178
    Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 5, 2016
    Assignee: Cooledge Lighting, Inc.
    Inventor: Michael A. Tischler
  • Patent number: 9230873
    Abstract: A semiconductor package resin composition of the present invention includes an epoxy resin, a curing agent, inorganic particles, nano-particles surface treated with a silane that contains a photopolymerizable functional group, and a photopolymerization initiator.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 5, 2016
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Kohichiro Kawate, Hiroko Akiyama, Naota Sugiyama, Brant U. Kolb, Eric G. Larson
  • Patent number: 9224896
    Abstract: A photoelectric conversion material is disclosed in the present invention and comprises at least a cone material. The cone material is composed of an isomer and comprises a plurality of grains. The sizes of the grains are arranged from smaller ones to larger ones along a direction. In the meantime, a method for fabricating the above photoelectric conversion material is also disclosed here. The method comprises the following steps. First, a precursor is provided. The precursor comprises at least a cone material and the cone material is a multilayer structured material, such as sodium titanate and potassium titanate, formed by stacking first materials and second materials. And then, the precursor is annealed to let the second materials leave from the cone material, and the cone material becomes the above photoelectric conversion material with a plurality of grains.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: December 29, 2015
    Assignee: National Tsing Hua University
    Inventors: Chi-Young Lee, Hsin-Tien Chiu, Po-Chin Chen, Min-Chiao Tsai
  • Patent number: 9219128
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata Camillo-Castillo, David L. Harame, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 9209114
    Abstract: Disclosed herein is a power module package including an external connection terminal, a substrate in which a fastening unit allowing one end of the external connection terminal to be insertedly fastened thereinto is formed to penetrate in a thickness direction thereof, and a semiconductor chip mounted on one surface of the substrate.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 8, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do Jae Yoo, Young Ki Lee, Bum Seok Suh, Joon Seok Chae
  • Patent number: 9209235
    Abstract: An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a pixel-defining layer (PDL) disposed on the TFT and comprising a first area having a first thickness and a second area having a second thickness greater than the first thickness, and a via hole in the first area; a pixel electrode disposed on at least a portion of the first area, and electrically connected to the TFT via the via hole; an intermediate layer on the pixel electrode, the intermediate layer comprising an emission layer (EML); and an opposite electrode on the intermediate layer. According to a method of manufacturing the organic light emitting display apparatus, the PDL is formed on the substrate and then the pixel electrode is formed on the first area.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 8, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chang-Min Kang
  • Patent number: 9202698
    Abstract: Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Vamsi K. Paruchuri
  • Patent number: 9202788
    Abstract: A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yasutoshi Okuno, Yi-Tang Lin
  • Patent number: 9196589
    Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 24, 2015
    Assignee: XINTEC INC.
    Inventors: Yu-Lin Yen, Hsi-Chien Lin, Yeh-Shih Ho
  • Patent number: 9196522
    Abstract: A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu