Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A semiconductor device has a supply pad to which a supply voltage is fed, a supply conductor that is electrically connected to the supply pad, an input/output pad via which a signal is fed in from outside or fed out to outside, an electrostatic protection device that is electrically connected to the input/output pad and that is electrically connected via the supply conductor to the supply pad, and an internal circuit that is electrically connected via a signal conductor to the input/output pad. The electrostatic protection device, the input/output pad, and the internal circuit are arranged in this order from edge to center of the semiconductor device.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract: An amorphous-silicon photoelectric device and a fabricating method thereof are disclosed. The amorphous-silicon photoelectric device includes: a substrate; a thin-film transistor and a photosensor with the photodiode structure, which are provided at different positions on the substrate; and a contact layer; in which the contact layer is located below the photosensor, and the contact layer is partially covered by the photosensor, moreover, the contact layer and the gate-electrode layer in the thin-film transistor are provided in a same layer and of a same material. According to the technical solutions of the present disclosure, the fabricating procedure of an a-Si photoelectric device can be simplified, thereby improving the fabrication efficiency and reducing costs.

Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Abstract: A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.

Abstract: Fabrication methods of a transparent conductive electrode (301) and an array substrate are provided. The fabrication method of the transparent conductive electrode (301) comprises: forming a sacrificial layer pattern (201) on a substrate (10) having a first region (A1) and a second region (A2) adjacent to each other, wherein the sacrificial layer pattern (201) is located in the second region (A2), and has an upper sharp corner profile formed on a side adjacent to the first region (A1); forming a transparent conductive thin-film (30) in the first region (A1) and the second region (A2) of the substrate (10) with the sacrificial layer pattern (201) formed thereon, wherein a thickness ratio of the transparent conductive thin-film (30) to the sacrificial layer pattern (201) is less than or equal to 1:1.

Abstract: A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.

Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.

Abstract: A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: The present disclosure relates to a method for manufacturing a display device and a method for repairing the display device, and further relates to a liquid crystal display panel including the display device. The method for manufacturing a display device comprises the following steps: (a) forming a gate, a scanning line, a first insulation layer, and a semiconductor layer on a substrate in sequence; (b) determining the position of a data line on the semiconductor layer, and providing an etch stop layer on the semiconductor layer at a place deviating from the data line; (c) modifying the semiconductor layer at the position of the data line into a conductor; and (d) arranging a source, a drain, the data line, and a second insulation layer on the semiconductor layer. This method can repair the data line by welding the segments of the broken data line onto the conductor layer beneath the data line.

Abstract: A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The method for manufacturing the array substrate comprises: forming a pattern of an active layer of a switching thin-film transistor (TFT) and a pattern of a corresponding pixel electrode on a base substrate, in which the active layer of the switching TFT and the pixel electrode are on the same layer.

Abstract: LED dies are suspended in an ink and printed on a first support substrate to form a light emitting layer having a light emitting surface emitting primary light, such as blue light. A mixture of a transparent binder, phosphor powder, and transparent glass beads is formed as an ink and printed over the light emitting surface. The mixture forms a wavelength conversion layer when cured. The beads are preferably sized so that the tops of the beads protrude completely through the conversion layer. Some of the primary light passes through the beads with virtually no attenuation or backscattering, and some of the primary light is converted by the phosphor to secondary light. The combination of the secondary light and the primary light passing though the beads may form white light. The overall color is highly controllable by controlling the percentage weight of the beads.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.

Abstract: A light emitting diode (LED) having well and/or barrier layers with a superlattice structure is disclosed. An LED has an active region between an N-type GaN-based semiconductor compound layer and a P-type GaN-based semiconductor compound layer, wherein the active region comprises well and/or barrier layers with a superlattice structure. As the well and/or barrier layers with a superlattice structure are employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer.

Abstract: On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region.

Abstract: Disclosed are a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad.