Patents Examined by Hsin-Yi Hsieh
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Patent number: 10396157Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.Type: GrantFiled: March 6, 2018Date of Patent: August 27, 2019Assignee: United Microelectronics Corp.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 10388517Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.Type: GrantFiled: July 16, 2012Date of Patent: August 20, 2019Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
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Patent number: 10388783Abstract: Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.Type: GrantFiled: February 17, 2016Date of Patent: August 20, 2019Assignee: Polar Semiconductor, LLCInventor: Don Rankila
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Patent number: 10374116Abstract: A light receiving and emitting element module includes a wiring substrate; a light emitting element and a light receiving element which are disposed on the wiring substrate; and a lens member having a lens portion, a support portion configured to support the lens portion disposed above the light emitting element and the light receiving element and a column disposed on a lower surface of the support portion, wherein a tip end of the column is in contact with an upper surface of the wiring substrate.Type: GrantFiled: April 27, 2016Date of Patent: August 6, 2019Assignee: KYOCERA CorporationInventor: Naoki Fujimoto
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Patent number: 10361334Abstract: An avalanche photodiode detector is provided with a substrate including an array of avalanche photodiodes. An optical interface surface of the substrate is arranged for accepting external input radiation. There is provided at least one cross-talk blocking layer of material including apertures positioned to allow external input radiation to reach photodiodes and including material regions positioned for attenuating radiation in the substrate that is produced by photodiodes in the array. Alternatively at least one cross-talk blocking layer of material is disposed on the optical interface surface of the substrate to allow external input radiation to reach photodiodes and attenuate radiation in the substrate that is produced by photodiodes in the array. At least one cross-talk filter layer of material can be disposed in the substrate adjacent to the photodiode structures, including a material that absorbs radiation in the substrate that is produced by photodiodes in the array.Type: GrantFiled: December 31, 2014Date of Patent: July 23, 2019Assignee: Massachusetts Institute of TechnologyInventors: K. Alexander McIntosh, David C. Chapman, Joseph P. Donnelly, Douglas C. Oakley, Antonio Napoleone, Erik K. Duerr, Simon Verghese, Richard D. Younger
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Patent number: 10355006Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells, a first film, and a second film. The memory cells are placed at intervals in a first direction on a semiconductor substrate. The first film is placed continuously in the first direction above the memory cells so as to cover all of the memory cells and including mainly metal oxide. The second film is placed on the first film and including mainly silicon nitride or silicon dioxide.Type: GrantFiled: January 19, 2016Date of Patent: July 16, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ryota Fujitsuka, Nobuhito Kuge, Kensei Takahashi
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Patent number: 10347724Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.Type: GrantFiled: December 7, 2015Date of Patent: July 9, 2019Assignee: Mitsubishi Electric CorporationInventors: Rina Tanaka, Katsutoshi Sugawara, Yasuhiro Kagawa, Naruhisa Miura
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Patent number: 10319734Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.Type: GrantFiled: January 20, 2016Date of Patent: June 11, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Akifumi Gawase, Kei Watanabe, Shinya Arai
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Patent number: 10297692Abstract: The invention provides a manufacturing method of TFT substrate and a TFT substrate. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.Type: GrantFiled: June 23, 2016Date of Patent: May 21, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhichao Zhou, Hui Xia
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Patent number: 10290773Abstract: A light-emitting device is disclosed and comprises: a substrate; a light-emitting stack comprising a first conductivity type semiconductor layer, an active layer over the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer over the active layer; a transparent conductive layer over the a light-emitting stack; a first trench dividing the transparent conductive layer into a first block and a second block; a connecting layer electrically connecting the two blocks of the transparent conductive layer; a first conductivity type contact layer between the substrate and the first conductivity type semiconductor layer, wherein the conductivity of the first conductivity type contact layer is greater than the conductivity of the first conductivity type semiconductor layer.Type: GrantFiled: September 13, 2012Date of Patent: May 14, 2019Assignee: EPISTAR CORPORATIONInventors: Chen Ou, Liang Sheng Chi, Chun Wei Chang, Chih-Wei Wu
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Patent number: 10283673Abstract: A light emitting device is provided. The light emitting device includes a first semiconductor layer, an active layer including a plurality of well layers and a plurality of barrier layers on the first semiconductor layer, a second semiconductor layer on the active layer, and an electrode layer on the second semiconductor layer. A top surface of a first barrier layer adjacent to the second semiconductor layer includes an uneven surface and has a larger area than an area of a top surface of a second barrier layer, wherein the first barrier layer has a thickness thicker than a thickness of the second barrier layer.Type: GrantFiled: June 26, 2014Date of Patent: May 7, 2019Assignee: LG Innotek Co., Ltd.Inventors: Oh Min Kwon, Jong Pil Jeong
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Patent number: 10269821Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.Type: GrantFiled: February 17, 2016Date of Patent: April 23, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masao Shingu, Katsuyuki Sekine, Hirokazu Ishigaki, Makoto Fujiwara
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Patent number: 10269791Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.Type: GrantFiled: January 20, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Ling-Yen Yeh, Yuan-Chen Sun
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Patent number: 10249734Abstract: A poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The method for manufacturing a poly-silicon thin film transistor includes forming a poly-silicon layer on a base substrate so that the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; forming a barrier layer between a gate electrode and a gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and with the barrier layer as a mask doping the second poly-silicon areas to form lightly doped areas. By this method, the lightly doped areas may have the same length, and thus the problem of excessive leakage current is avoided.Type: GrantFiled: August 21, 2014Date of Patent: April 2, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xiaohui Jiang, Jiaxiang Zhang
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Patent number: 10217641Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.Type: GrantFiled: January 20, 2016Date of Patent: February 26, 2019Assignees: International Business Machines Corporation, MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: William J. Gallagher, Marinus Johannes Petrus Hopstaken, Ko-Tao Lee, Tomas Palacios, Daniel Piedra, Devendra K. Sadana
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Patent number: 10199253Abstract: A method of manufacturing a semiconductor device includes disposing a peel-off layer on the second surface of the first substrate, wherein the second surface of the first substrate comprises semiconductor integrated circuits, and the peel-off layer does not extend to an outer peripheral portion of the first substrate, bonding a second substrate to the peel-off layer via a bonding layer, attaching a tape onto the first surface of the first substrate, wherein the tape comprises an adhesive agent having an adhesive strength capable of being lowered by UV irradiation, irradiating a portion of the adhesive agent provided at the outer peripheral portion with UV rays directed toward the first surface, and separating the first substrate from the second substrate at the adhesive agent portion and the peel-off layer portion.Type: GrantFiled: March 2, 2015Date of Patent: February 5, 2019Assignee: Toshiba Memory CorporationInventors: Masaya Shima, Kenji Takahashi
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Patent number: 10186547Abstract: Provided are a solid-state imaging element which can be simply manufactured and can control movement of electric charges in an accumulation region with a high degree of accuracy, and a method of manufacturing the same. A solid-state imaging element (1a) includes a substrate (11) having a first conductivity type; an accumulation region (12) having a second conductivity type and provided in the substrate (11); a read-out region (13) for receiving the transferred electric charges accumulated in the accumulation region (12); and a transfer section (14) for transferring the electric charges from the accumulation region (12) to the read-out region (13). An impurity concentration modulation region 121 having a locally high concentration of an impurity having the second conductivity type, or having a locally low concentration of an impurity having the first conductivity type is formed in a part of the accumulation region (12).Type: GrantFiled: February 21, 2013Date of Patent: January 22, 2019Assignee: SHARP KABUSHIKI KAISHAInventor: Takeo Ushinaga
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Patent number: 10163856Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.Type: GrantFiled: October 30, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen Hsin Wei
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Patent number: 10163698Abstract: A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure.Type: GrantFiled: May 7, 2014Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Fu Yeh, Ming-Han Lee
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Patent number: 10147843Abstract: A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure is disposed between a window layer and a light-directing structure. The light-directing structure is configured to direct light toward the window layer; examples of suitable light-directing structures include a porous semiconductor layer and a photonic crystal. An n-contact is electrically connected to the n-type region and a p-contact is electrically connected to the p-type region. The p-contact is disposed in an opening formed in the semiconductor structure.Type: GrantFiled: July 24, 2008Date of Patent: December 4, 2018Assignee: LUMILEDS LLCInventors: John Epler, James G. Neff, Oleg B. Shchekin