Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.

Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer.

Abstract: A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An upper surface of the molding material is recessed from an upper surface of the through via. A dielectric layer is deposited over the through via and the molding material. The dielectric layer has a first upper surface with a first variation in height between a first area disposed over the through via and a second area disposed over the molding material. Exposure processes are performed on the dielectric layer. The dielectric layer is developed. After the developing, the dielectric layer has a second upper surface with a second variation in height between the first area and the second area. The first variation is greater than the second variation.

Abstract: A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the first conductor region and the second conductor region. The path comprises a first semiconductor volume having a non-uniform distribution of ions and a second semiconductor volume having a uniform distribution of ions relative to the first semiconductor volume.

Abstract: A MEMS sensor and a manufacturing method thereof is provided: forming a lower electrode layer wherein a metal is deposited on a portion of a lower glass substrate; forming a structural layer by etching according to a pattern which is formed on an upper surface of a silicon wafer and then further etching to the same thickness as the metal which is formed on a portion of the lower electrode layer; anodic bonding the structural layer to an upper portion of the lower electrode layer formed; forming a sensing part in the structural layer by etching according to a pattern which is formed on an opposite surface of the structural layer which is not etched; and forming an upper electrode layer by depositing a metal on an upper wafer and eutectic bonding the upper electrode layer to the structural layer on which the sensing part is formed.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

Abstract: Provided is a light emitting module in which an LED device is mounted and power is supplied to the LED device by a gold wire. The light emitting module includes a first resin (sealing material) that seals the gold wire and a second resin (dam wall) that surrounds at least a portion of the outer peripheral of the first resin. The first resin has a lower viscosity and a lower elastic modulus compared to the second resin, and protects the gold wire mechanically and chemically. The second resin suppresses the first resin from being flowed out toward the peripherals, and, as a result, the sealing state of the gold wire by the first resin may be maintained.

Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.

Abstract: A thin film transistor and a method for manufacturing the same, an array substrate including the thin film transistor, and an electronic apparatus including the thin film transistor or provided with the array substrate. The thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode, the active layer is formed of a mixture including a semiconductor nano-material and a photoresist material. The method for manufacturing the thin film transistor includes: preparing a mixture including a semiconductor nano-material and a photoresist material; applying the mixture over a substrate, and forming a patterned active layer by exposure and development.

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

Abstract: Disclosed are a method of fabricating a light emitting diode and a light emitting diode fabricated by the same. In the method of fabricating a light emitting diode, a convex-concave pattern is formed on a light emitting structure and a nanosphere layer is transferred to the convex-concave pattern, followed by dry etching to form a stepped surface structure having a plurality of nanobumps arranged on a surface thereof, and chemical coating to reduce surface energy of the stepped surface structure. The method can easily form a stepped surface structure having a plurality of nanobumps on a surface of a convex-concave pattern periodically arranged through nanosphere lithography and dry etching, thereby simplifying the fabrication process while improving production yield.

Abstract: A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

Abstract: A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.