Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

Abstract: In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.

Abstract: A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.

Abstract: Imaging systems may include camera modules that include multiple image sensor pixel arrays. A transparent lens substrate may be formed over the image pixel arrays. Lenses may be formed in the lens substrate such that each lens transmits light to a corresponding image sensor pixel array. Total internal reflection mitigation structures such as groove structures may be formed in one or more surfaces of the lens substrate between each of the lenses. The groove structures may include concentric ring shaped grooves in a surface of the lens substrate so that each lens is surrounded by a respective group of concentric ring shaped grooves. The groove structures may have a depth, angle, shape, and spacing that prevents total internal reflection of image light between the lenses so that high incident angle image light incident on a given pixel array is not captured by an adjacent pixel array.

Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step.

Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the first conductor region and the second conductor region. The path comprises a first semiconductor volume having a non-uniform distribution of ions and a second semiconductor volume having a uniform distribution of ions relative to the first semiconductor volume.

Abstract: A MEMS sensor and a manufacturing method thereof is provided: forming a lower electrode layer wherein a metal is deposited on a portion of a lower glass substrate; forming a structural layer by etching according to a pattern which is formed on an upper surface of a silicon wafer and then further etching to the same thickness as the metal which is formed on a portion of the lower electrode layer; anodic bonding the structural layer to an upper portion of the lower electrode layer formed; forming a sensing part in the structural layer by etching according to a pattern which is formed on an opposite surface of the structural layer which is not etched; and forming an upper electrode layer by depositing a metal on an upper wafer and eutectic bonding the upper electrode layer to the structural layer on which the sensing part is formed.

Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer.

Abstract: A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An upper surface of the molding material is recessed from an upper surface of the through via. A dielectric layer is deposited over the through via and the molding material. The dielectric layer has a first upper surface with a first variation in height between a first area disposed over the through via and a second area disposed over the molding material. Exposure processes are performed on the dielectric layer. The dielectric layer is developed. After the developing, the dielectric layer has a second upper surface with a second variation in height between the first area and the second area. The first variation is greater than the second variation.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

Abstract: Provided is a light emitting module in which an LED device is mounted and power is supplied to the LED device by a gold wire. The light emitting module includes a first resin (sealing material) that seals the gold wire and a second resin (dam wall) that surrounds at least a portion of the outer peripheral of the first resin. The first resin has a lower viscosity and a lower elastic modulus compared to the second resin, and protects the gold wire mechanically and chemically. The second resin suppresses the first resin from being flowed out toward the peripherals, and, as a result, the sealing state of the gold wire by the first resin may be maintained.

Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: A thin film transistor and a method for manufacturing the same, an array substrate including the thin film transistor, and an electronic apparatus including the thin film transistor or provided with the array substrate. The thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode, the active layer is formed of a mixture including a semiconductor nano-material and a photoresist material. The method for manufacturing the thin film transistor includes: preparing a mixture including a semiconductor nano-material and a photoresist material; applying the mixture over a substrate, and forming a patterned active layer by exposure and development.