Abstract: A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacers, and within the respective recesses; and f) providing a

Abstract: In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving providing a structure comprising a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer, and a mask layer over the silicon device layer; etching portions of the mask layer, the silicon device layer, and the buried insulation layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried insulation layer and to form gaps at least partially surrounded by the polysilicon sidewalls; depositing an insulation material in the gaps; and removing the mask layer.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: Epitaxial silicon layers are formed on n+-source/drain regions of two MOS transistors neighboring to each other and formed on a silicon substrate, respectively. In this processing, polycrystalline silicon pieces are generated on an element isolating and insulating film and others. Thereafter, the silicon substrate is exposed to an oxygen atmosphere so that hydrogen reacts with silicon at the surfaces of the epitaxial silicon layers and the surfaces of the polycrystalline silicon pieces to form silicon oxide films and polycrystalline silicon pieces. Thereby, short-circuit between MOS transistors in neighboring memory cells is prevented, and a semiconductor device has a high electrical reliability.

Abstract: A semiconductor device includes a substrate and a plurality of interconnect metallization lines defined over the substrate, each interconnect metallization line being provided with an electromigration-impeding composition including a percentage by weight of aluminum, a percentage by weight of copper, and a percentage by weight of zinc. The percentage by weight of zinc may be less than about 4 in solid solution in Al at 100 degrees C, which is a substantial increase in the Zn content over the about 0.5 weight percent of the Cu content in previously-used Al—Cu alloys. The percentage by weight of Zn may preferably range between about 1 and 2. The electromigration-impeding composition of the lines may include a structure of a solid solution of Al and Zn in the form of grains. The grains are bounded by grain boundaries. The structure further includes a precipitate of Al and Cu defined in the grain boundaries.

Abstract: A semiconductor device and a method of producing the same are disclosed. After boron or similar p-type impurity has been introduced into a polysilicon layer constituting a pMOS gate, annealing can be effected at an optimal temperature low enough to prevent the impurity from entering a silicon substrate via a gate oxide film, e.g., 800° C. or below in the case of boron. This prevents the characteristic of a transistor, e.g., threshold voltage from being varied. Further, in an nMOS gate electrode and source-drain region, the n-type impurity can be provided with a concentration reducing the resistance of a silicide layer. In addition, in the emitter diffusion layer of a bipolar transistor, the concentration of the n-type impurity does not fall and allows a current amplification factor to be increased while allowing an emitter resistance to be reduced.

Abstract: A semiconductor device includes a semiconductor element provided on a substrate, a lead-in wiring electrically provided on a substrate, a lead-in wiring electrically connected with the electrode of the semiconductor element, a barrier metal film for covering the lead-in wiring surface for protecting the lead-in wire, wherein the section of the lead-in wiring is inversely trapezoidal in shape vertial to the lengthwise direction of the lead-in wiring.

Abstract: The present invention provides a semiconductor device capable of improving a withstand voltage for a wire placed in the neighborhood of a contact. When the direction in which a wiring layer extends in the direction of a plane as viewed from the top of a substrate, is defined as a first direction, the direction orthogonal to the first direction on the plane is defined as a second direction, a radius of curvature of a conductive material layer closest to the opening is defined as R, a point where the conductive material layer and an end of the wiring layer intersect, is defined as X, a point where a straight line extending along the second direction from the point X intersects a straight line extending along the first direction through the center of the radius R of curvature of the conductive material layer, is defined as Y, and the distance between the points X and Y as viewed in the second direction is defined as A, the relations in COS−1(A/R)>46 are established.

Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: Disclosed are flat/vertical type vacuum field transistor (VFT) structures, which adopt a MOSFET-like flat or vertical structure so as to increase the degree of integration and can be operated at low operation voltages at high speeds. The flat type comprises a source and a drain, made of conductors, which stand at a predetermined distance apart on a thin channel insulator with a vacuum channel therebetween; a gate, made of a conductor, which is formed with a width below the source and the drain, the channel insulator functioning to insulate the gate from the source and the drain; and an insulating body, which serves as a base for propping up the channel insulator and the gate.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer.

Abstract: In a method for forming a high aspect ratio structure using copper in an ultra high-speed device, the degree of copper burying is heightened. A high aspect ratio structure, such as a fine connecting hole, is formed in a layer insulating film on a silicon substrate. Then, after a CVD-TiN film is formed to have a thickness of 10 nm on the insulating film, a copper film having a thickness of 1 &mgr;g m is formed. In this case, the highly pure copper film is formed by controlling film-forming conditions so as to set oxygen and sulfur concentrations in the film equal to a fixed level or lower. Thus, during its burying in the connecting hole, the surface diffusibility and fluidity of the copper film heated by means of laser irradiation are facilitated.

Abstract: A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.

Abstract: A through hole passes through an interlayer isolation film and an antireflection film, to partially expose a surface of a first wiring layer. A clearance filling member fills up a clearance under an inner edge of the antireflection film. A barrier metal film continuously covers the exposed surface of the first wiring layer, an inner wall surface of the through hole and a surface of the interlayer isolation film. Passing through the through hole, a second wiring layer is connected with the first wiring layer through the barrier metal film. Thus provided is a method of fabricating a semiconductor device improved to be capable of avoiding disconnection of a wire in a through hole.

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Abstract: A capacitor structure having a first and at least a second level of electrically conductive concentric lines of an open-loop configuration. The conductive lines of the at least second level overlie the conductive lines of the first level. A dielectric material is disposed between the first and second levels of conductive lines and between the conductive lines in each of the first and second levels. The conductive lines are electrically connected in an alternating manner to terminals of opposing polarity so that capacitance is generated between adjacent lines in each level and in adjacent levels. The capacitor especially useful in deep sub-micron CMOS.

Abstract: Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic etching through holes opened at specific intervals. Then the opened holes are filled with an insulating film, and cavities are formed. In the upper part of the cavity, a signal line of the second metal layer is formed. As a result, a semiconductor device is provided by the CMP flattening technology without being accompanied by increase of parasitic capacity between signal lines by metal dummy patterns or shorting due to dust and the like.