Abstract: The MOS transistor incorporated in a semiconductor device comprises a gate electrode formed on a semiconductor substrate through the medium of a gate insulating film, a first impurity introduced area of an LDD structure composed of a low-concentration impurity area and a high-concentration impurity area formed on the semiconductor substrate on one side of the gate electrode, and a second impurity introduced area composed solely of a high-concentration impurity area formed on the semiconductor substrate on the other side of the gate electrode.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.

Abstract: A semiconductor device including a trench element separation structure and adapted to a high degree of integration without having crystal defects produced in a semiconductor substrate, and a method of manufacturing the same. The semiconductor device includes a trench element separation region in a prescribed region of the semiconductor substrate, the wall of the semiconductor substrate which forms an inside surface of a trench is covered with a first insulation film, and a second insulation film and a third insulation film are filled inside the trench being stacked in layers in this order.

Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Abstract: A semiconductor device includes a protective circuit at an input/output port thereof, wherein the protective circuit includes a plurality of protective MOS transistors. A diffused region is disposed between the n-type source/drain regions and a guard ring formed in a p-well for encircling the source/drain regions of the protective transistors. The diffused region is of lightly doped p-type or of an n-type and increases the resistance of a parasitic bipolar transistor formed in association with the protective transistors. The increase of the resistance assists protective function of the protective device against an ESD failure of the internal circuit of the semiconductor device.

Abstract: A via is formed in a semiconductor device using a self-aligned copper-based pillar to connect upper and lower copper interconnect layers separated by a dielectric. The lower interconnect layer is formed on an underlying layer. The copper-based via pillar is formed on the lower interconnect layer. The upper interconnect layer is formed to make electrical contact to the exposed upper surface of the via pillar. Conductive diffusion barrier material is formed on vertical sidewalls of the lower interconnect layer.

Abstract: A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer 2; a barrier layer 4; a conductive layer 5; a barrier layer 6 having an opening 11; an insulating layer 7 having a through hole 8 exposing a surface of conductive layer 5 and a part of a surface of barrier layer 6; a barrier layer 9 formed on a surface of said through hole 8 and insulating layer 7 which is in contact with an upper surface 6a of barrier layer 6; and a conductive layer 10 filling opening 11 and through hole 8.

Abstract: A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.

Abstract: Method and structures for making a highly reliable metal interlock structure with continuous via and line structures. The absence of barrier layers between vias and lines or absence of interlevel dielectric layer is used to enhance chip performance.

Abstract: An improved series-connected transistor architecture and a method for forming the same are provided. Gate conductors for series connected transistors are patterned such that gate conductors on either side of a merged source/drain region which will not be contacted in the completed circuit are spaced more closely together than other gate conductors. In an embodiment of the method, these closely-spaced gate conductors have a spacing between facing sidewalls of less than about twice the expected sidewall spacer width for the process. After a first dopant impurity introduction, a conformal dielectric layer is deposited and portions of the dielectric layer are removed to form sidewall spacers. In the region between the closely-spaced gate conductors, the spacers are merged to form a continuous dielectric. This dielectric protects the substrate between the closely-spaced gate conductors from subsequent impurity introduction and salicide processes.

Abstract: A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element.

Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: A new liner structure and method to incorporate this liner into process flows in order to lower the processing temperature of aluminum extrusion or reflow cavity filling. The structures produced by this innovative method are particularly useful for advanced sub-quarter micron multi-level interconnect applications.

Abstract: A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad.

Abstract: A metal-oxide semiconductor device having an enhanced compatibility for use as a complementary device comprises an additional lateral well region interposed between the source and drain region of the device. In one embodiment, the invention comprises a p-channel DMOS which may be integrated simultaneously on a chip with an n-channel DMOS, the p-channel DMOS having an n-type substrate, an upper self-aligned region disposed in a well region of p-type conductivity, a p-type impurity region disposed in the upper well, the well region of p-type conductivity being interposed between the n-substrate and the n-well region. A double-diffused CMOS structure may be fabricated by adding one implantation step to present technology involving fabrication of n-channel devices.

Abstract: A main electrode region of a semiconductor element is provided in a semiconductor region on the surface of a semiconductor substrate, and first and second interlayer insulating films are deposited on this semiconductor region. A metal interconnection is provided on top of the second interlayer insulating film. The main electrode region and the metal interconnection a shape having a first tapered portion with an isotropic taper angle &thgr;3, which starts from the interface between the first and second interlayer insulating films, and a second tapered portion with an anisotropic taper angle &thgr;4, which starts from a point within the second interlayer insulating film. As a result, the shape of the face of the contact plug connecting to the metal interconnection is anisotropic, having dimensions which are greater in the direction parallel to the metal interconnection than in the direction perpendicular to the metal interconnection.

Abstract: A cavity structure formed in a semiconductor substrate and under a device formation region on which a device is formed. The cavity structure has supporting pillars providing the device formation region with mechanical strength.

Abstract: A p-type silicon substrate has an element isolation region of an STI structure formed therein. A transistor region isolated by the isolation region has a n-type source/drain diffusion layer. Further, a p-channel impurity layer is formed substantially only in its channel region for controlling its threshold voltage (Vth). A gate insulator film consisting of a high dielectric film is formed on the channel region with an Si3N4 film interposed therebetween. A metal gate electrode having its bottom and side surfaces covered with the gate insulator film is provided in a self-alignment manner with respect to the source/drain diffusion layer.

Abstract: A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.