Abstract: A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

Abstract: A device that detects single optical and radiation events and that provides improved blue detection efficiency and lower dark currents than prior silicon SSPM devices. The sensing element of the devices is a photodiode that may be used to provide single photon detection through the process of generating a self-sustained avalanche. The type of diode is called a Geiger photodiode or signal photon-counting avalanche diode. A CMOS photodiode can be fabricated using a “buried” doping layer for the P-N junction, where the high doping concentration and P-N junction is deep beneath the surface, and the doping concentration at the surface of the diode may be low. The use of a buried layer with a high doping concentration compared to the near surface layer of the primary P-N junction allows for the electric field of the depletion region to extend up near the surface of the diode. With a low doping concentration through the bulk of the diode, the induced bulk defects are limited, which may reduce the dark current.

Abstract: A method of forming semiconductor fins is provided. Sacrificial fins are provided on a surface of substrate. A hard mask layer, formed around the sacrificial fins and the gaps therebetween, is made coplanar with a topmost surface of the sacrificial fins. A fin cut mask then covers a portion of the sacrificial fins and partly covers a sacrificial fin. Trenches are formed in the hard mask layer by removing sacrificial fins not covered by the fin cut mask and that portion of the sacrificial fin not partly covered by the fin cut mask. Spacers are formed on the sidewalls of the trenches and a plug is formed in the trench formed by removing that portion of the sacrificial fin not partly covered by the fin cut mask. Semiconductor fins are grown epitaxially in the trenches having the spacers from the exposed surface of the substrate upward.

Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region selectively provided on the first semiconductor region; a third semiconductor region selectively provided on the second semiconductor region; a first electrode provided on the third semiconductor region and connected to the third semiconductor region; a second electrode electrically connected to the first semiconductor region; a third electrode provide via an insulating film on the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a fourth electrode provided on the second electrode side of the third electrode, the fourth electrode being provided via the insulating film on the first semiconductor region. The insulating film has three or more regions between the fourth electrode and the first semiconductor region.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.

Abstract: A device layer of an integrated circuit device includes a semiconductor active layer spanning a plurality of device regions. Each of the device regions has a heating element, a temperature sensor, and bioFETs in the device layer. The bioFETs have source/drain regions and channel regions in the semiconductor active layer and fluid gates exposed on a surface for fluid interfacing on one side of the device layer. A multilayer metal interconnect structure is disposed on the opposite side of the device layer. This structure places the heating elements in proximity to the fluid gates enabling localized heating, precision heating, and multiplexed temperature control for multiplexed bio-sensing applications.

Abstract: A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer.

Abstract: A power MOSFET includes a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface. The power MOSFET further includes a field electrode in a field plate trench in the main surface. The field plate trench has an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface. The gate electrode includes a gate electrode material which comprises a metal.

Abstract: A flexible organic light emitting display and a method for manufacturing the same are disclosed. The method is: sequentially forming a first buffer layer, a switch array layer, a display unit layer, and a thin film package layer on a flexible underlay substrate. When the flexible organic light emitting display bends along the flexible underlay substrate, a first bending deformation force is generated. The first buffer layer is used to absorb the first bending deformation force, and the material of the first buffer layer is an organic insulating material.

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first stacked body; a semiconductor film; a charge storage film; and a second stacked body. The first stacked body includes: a plurality of first insulating layers; and a plurality of electrode layers. The second stacked body includes: a plurality of second insulating layers; a first insulating film provided between the plurality of second insulating layers and including a material different from that of the plurality of first insulating layers, the plurality of second insulating layers, and the plurality of electrode layers; and a second insulating film provided between the first insulating film and the substrate via the plurality of second insulating layers, including a same material as the first insulating film, and having lower film density than the first insulating film.

Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

Abstract: Disclosed is an organic electroluminescent display device, a method for manufacturing the same and a display apparatus. The organic electroluminescent display device comprises: a substrate; a thin film transistor disposed on the substrate and including a gate electrode and an active layer insulated with each other, and a source electrode and a drain electrode connected with the active layer; and an organic electroluminescent structure disposed on the substrate and including an anode, a luminescent layer and a cathode stacked sequentially, the anode and the drain electrode being electrically connected with each other. The anode and the active layer are disposed in the same layer. The active layer is made of a transparent oxide semiconductor material. The anode is made of the transparent oxide semiconductor material undergone a plasma treatment.

Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent.

Abstract: A stacked semiconductor device is provided in the present invention. The stacked semiconductor device includes a first substrate and a second substrate. A first conductive pad is disposed on the first substrate. A conductive pillar contacts the first conductive pad. At least one first barrier layer is disposed inside the conductive pillar. The conductive pillar encapsulates the first barrier layer. The elastic modulus of the first barrier layer is different from the elastic modulus of conductive pillar. A second conductive pad is disposed on the second substrate. A solder bump is disposed between the first substrate and the second substrate. The solder bump electrically connects to the conductive pillar. The conductive pillar can optionally include a truncated cone.

Abstract: Pixel arrays of an image sensor that include a first pixel and a second pixel adjacent the first pixel are provided. The first pixel may include a first photoelectric conversion device, a first charge storage device, a first floating diffusion node and a first transfer gate. The second pixel may include a second photoelectric conversion device, a second charge storage device, a second floating diffusion node and a second transfer gate. The pixel arrays may also include a storage gate on both the first charge storage device and the second charge storage device. The storage gate may have a unitary structure.

Abstract: Various embodiments relate to an optoelectronic component, including a carrier element, on which at least one optoelectronic semiconductor chip is arranged, and a cover, which is mounted on the carrier element in a region extending circumferentially around the semiconductor chip and together with the carrier element forms a sealed cavity in which the at least one optoelectronic semiconductor chip is arranged in an inert gas.