Abstract: Methods and systems for selecting a set of fast computable functions to assess core properties of entities are disclosed. A method includes: receiving a request to select a set of fast computable functions to determine core properties of an entity; determining, for each of a plurality of fast computable function nodes in a directed graph, a set of core property nodes in the directed graph that are connected to the fast computable function node; adding, to a solution set, a fast computable function node that is connected to a highest number of core property nodes that are currently unconnected to nodes in the solution set; repeating the adding until each of the core property nodes is connected to at least one of the nodes in the solution set; and outputting the fast computable function nodes in the solution set in response to the request.

Abstract: A method includes transforming, by a report connector according to at least one input mapping rule of the report connector, first input data received by a first application to create second input data for a specific report of a plurality of existing reports of a second application. The method also includes providing, by the report connector, the second input data to a report application programming interface (API) capable of providing an interface to the report of the second application. The method also includes receiving, by the report connector, first output data from the report API, the first output data based on the output data from the specific report of the second application. The method also includes transforming, by the report connector according to at least one output mapping rule of the report connector, the first output data to create second output data for the first application.

Abstract: A set of application programming interfaces (“APIs”) is provided that enables an application to perform operations on multiple system resources as a single logical unit of work through a transaction. The application can then commit or roll back the entire group of changes as a single unit in a coordinated manner. The APIs expose functions and methods that take a reference to a transaction context, such as a handle, name, or pointer, as one of their parameters so that the application can manipulate the resource as a transacted operation. The transaction is bound to all created handles so that all operations on the resource using those handles are also transacted. In an illustrative example, the set of APIs are transacted name-based WIN32 APIs that take a transaction handle. The transacted APIs expose transacted operations to the application for durable system resources in the OS kernel, including the NTFS file system (New Technology File System) and registry.

Abstract: A system and method of accessing functions includes running n-bit based code in an n-bit supporting system environment. An m-bit based provider object is instantiated in an m-bit hardware and operating system environment server. The provider object provides an interface between the n-bit based code and m-bit based server functions. m-bit based server functions are accessed from the n-bit based code via the m-bit based provider object.

Abstract: Computer-implemented methods, systems, and computer-readable storage media are disclosed to coordinate a plurality of devices in performing a task. A particular computer-implemented method includes storing updated status information at a device where the updated status information reflects a change in a vote for a task state of one or more of a plurality of devices. A first updated status message is sent to one or more of the plurality of devices where the first updated status message communicates the updated status information. A task consensus at the device is updated when the updated status information indicates that at least a predetermined quantity of the plurality of devices agrees on the task status.

Abstract: Processing an object that shares a parent with another object is disclosed. An indication is received with respect to an object that shares a parent object instance with one or more other objects that a change associated with the object is to be made to a data comprising the shared parent object instance. The parent object instance is cloned to create a new parent object instance. The new parent object instance is designated as the parent of the object instance.

Abstract: An information processing system capable of communicating with a printing apparatus which returns from power saving by external access, and having first and second access units adapted to access the printing apparatus, includes a requesting unit adapted to request notification of event occurrence generated by processing by the first access unit, and a determination unit adapted to determine the presence/absence of the notification of event occurrence. The second access unit accesses the printing apparatus, if the determination unit determines that there is the notification of the event occurrence.

Abstract: An approach for sharing data between a calling application and a callee application is presented. A callee application receives a request for processing data owned and stored by the calling application in a data table. The callee application receives a document to which containers that include data elements from the data table are attached in a predefined order. The callee application identifies element types corresponding to the containers based on a mapping interface table. The callee application unloads data elements from the containers into a data store via the predefined order and associates the data elements with the corresponding element types. The callee application processes the data according to the request. The processing includes applying a business rule to a data element based on the business rule being associated with an element type of the data element. Only the callee application has knowledge of the applied business rule.

Abstract: A method in a transaction management and financial services system configured to communicate between a server and at least one remote device via a network is described. The method can include the steps of receiving a referral from a referring party where the referral including information regarding any one of a financing-seeking party that has been declined by the referring party and a transaction management-seeking party; and storing the information regarding the referral in a storage device. Other methods performed by the integrated financial and transaction management services system are also described.

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.

Abstract: A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.

Abstract: Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: To store N bits of M?2 logical pages, the bits are interleaved and the interleaved bits are programmed to ?N/M? memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ?N/M? cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

Abstract: Systems and methods for protecting data in a tiered storage system are provided. The storage system comprises a management server, a media management component connected to the management server, a plurality of storage media connected to the media management component, and a data source connected to the media management component. Source data is copied from a source to a buffer to produce intermediate data. The intermediate data is copied to both a first and second medium to produce a primary and auxiliary copy, respectively. An auxiliary copy may be made from another auxiliary copy. An auxiliary copy may also be made from a primary copy right before the primary copy is pruned.

Abstract: A method for a removable media storage network environment that employs a media management system for managing a removable media system on behalf of client applications, and a media management agent to enhance the management of the removable media system by the media management system. The media management agent operates to determine an operational state of the removable media system, and to enhance an availability and a performance of the removable media system as managed by a media management system, wherein one or more one error recovery techniques are conditionally initiated based on the determined operational state of the removable media system and wherein the media management system is conditionally reconfigured based on the determined operational state of the removable media system.

Abstract: A technique synchronizes data retrieved from memory devices at a memory controller of a high-speed memory subsystem. Each memory device is organized into a plurality of data groupings. The memory controller stores (via one or more write operations) a known synchronization (sync) pattern at each data grouping on the memory devices and then retrieves (via one or more read operations) that sync pattern from the groupings. Synchronization logic located at a local clock boundary of the memory controller is configured to recognize the retrieved sync pattern and “automatically” synchronize all pieces of data retrieved from the data groupings, even though there may be substantial skew between the groupings.

Abstract: Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

Abstract: A serial-write, random-access read, memory addresses applications where the data in the memory may change more frequently than would make a PROM suitable, but that changes much less frequently than would require a RAM. This enables the circuit designer to optimize the memory for fast reads, and enables reads to be pipelined. One embodiment of the present invention provides a system that facilitates a serial-write, random-access read, memory. The system includes a plurality of memory cells and a serial access mechanism for writing data into the plurality of memory cells. The system also includes a parallel random-access mechanism for reading data from the plurality of memory cells.

Abstract: Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a size equal to or less than the second address space. The system execution area includes a control program having a first portion capable of addressing the first address space and the system execution space, a second portion constrained to address only the second address space and the system execution area, and at least one alias page. Responsive to a control program request for a first page in the virtual storage, a first frame is assigned in real storage corresponding to the page. Responsive to a request from the second portion of the control program for the first page, allocating an alias page in the system execution area, the alias page backed by the first frame.

Abstract: A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.