Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: An apparatus, system, and method are disclosed for servicing a data storage device. A service registration module registers a service process for servicing the stripe groups of a data storage device. A WIP map initialization module creates a WIP map for each stripe group of the service process. The stripe group selection module selects a stripe group and the service module performs the service process on the selected stripe group. The WIP map update module sets the WIP map entry of the selected stripe group. The stripe group selection module uses the WIP map to avoid the repeat selection of a stripe group to receive the service process. An I/O module may determine from the WIP map if a data block of a stripe group may be accessed during the service process and may direct the service process to the data block's stripe group out of turn to increase performance.

Abstract: A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

Abstract: A data structure design system for prolonging the life of an FRAM (Ferroelectric Random Access Memory) includes a CPU (Central Processing Unit) (1), an FRAM (2), an SDRAM (Synchronous Dynamic Random Access Memory) (3), and a clock (4). The FRAM is divided into a plurality of fixed-size blocks, and is for storing data. The SDRAM is for storing data that need to be written to the FRAM, and includes three data structures: queue one, queue two, and hash table. The CPU is for reading data from external storages, storing the data in the SDRAM, reading data from the SDRAM, and writing the data to the FRAM via the three data structures. The clock is for recording a predetermined time used to determine the blocks in the FRAM in which data have not been read up to the predetermined time. A related data structure design method is also provided.

Abstract: A method and system to detect an occurrence of a predetermined event within the system, and change a power state of a hard drive (HD) in response to the event, are described. In one embodiment, in response to detecting consecutive HD reads have been satisfied by a non-volatile cache (NVC) of the HD, for at least a predetermined period of time, or detecting that a predetermined quantity of consecutive HD reads have been satisfied by the NVC, spinning down the HD. In an alternative embodiment, in response to detecting a predetermined number of HD data transactions have been serviced by the NVC or the HD, canceling a planned spinning down of the HD or spinning up the HD.

Abstract: A storage device is provided with a file I/O interface control device and a plurality of disk pools. The file I/O interface control device sets one of a plurality of storage hierarchies defining storage classes, respectively, for each of LUs within the disk pools, thereby forming a file system in each of the LUs. The file I/O interface control device migrates at least one of the files from one of the LUs to another one of the LUs of an optimal storage class, based on static properties and dynamic properties of each file.

Abstract: Various embodiments of the present invention are directed to efficient provision, by a virtual-machine monitor, of a virtual, physical memory interface to guest operating systems and other programs and routines interfacing to a computer system through a virtual-machine interface. In one embodiment of the present invention, a virtual-machine monitor maintains control over a translation lookaside buffer (“TLB”), machine registers which control virtual memory translations, and a processor page table, providing each concurrently executing guest operating system with a guest-processor-page table and guest-physical memory-to-physical memory translations. In one embodiment, a virtual-machine monitor can rely on hardware virtual-address-translation mechanisms for the bulk of virtual-address translations needed during guest-operating-system execution, thus providing a guest-physical memory interface without introducing excessive overhead and inefficiency.

Abstract: Broadly speaking a method and an apparatus is provided for distributing commands to a digital data storage system. More specifically, the method and apparatus distributes read commands to a mirrored pair of disk drives in a substantially balanced manner. A read command having an associated starting address is received from an operating system. An address range is updated based on the starting address associated with the read command. A determination is made as to a portion of the address range containing the starting address associated with the read command. The read command is directed to be performed using a disk drive associated with the portion of the address range determined to contain the starting address.

Abstract: In a disk array system having a plurality of spare drives, the storage areas of which are not wasted without being influenced by the physical boundaries thereof. There is defined one large spare parity group 104 which is composed of a plurality of spare drives 103, 103, . . . , and so on. A spare logic drive 202 having the same capacity as that of a faulty data drive 101B is cut out from a large spare logic drive 201 provided by the spare parity group 104, and the data of the faulty data drive 101B are copied to the cut spare logic drive 202. A virtual physical drive 206 corresponding to the spare logic drive 202 is defined and is incorporated instead of the faulty data drive 101B into a data parity group 102A. As a result, data of the faulty data drive 101B are saved in the virtual physical drive 206 (or the spare logic drive 202).

Abstract: In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterable memories may be dynamically mapped.

Abstract: In one embodiment, the present invention provides a method for mirroring data representing a file system. The data is stored on a primary storage server and is mirrored on a secondary storage server. In the method the file system is mirrored without comparing blocks used to that represent the file system at the primary storage server, and the secondary storage server.

Abstract: A recording method includes the steps of reading a management table for managing whether data are recorded on a recording medium in units of a first recording segment; detecting whether the first recording segment is associated with a second recording segment smaller than the first recording segment according to a designation of data recording in units of the second recording segment into the recording medium; discriminating from data in the management table whether it is possible to read data of the first recording segment; reading the data in units of the first recording segment and temporarily recording the data to a memory when in the discriminating step it is determined that it is possible to read data in units of the first recording segment; recording data to a part of the first recording segment recorded in the memory in units of the second recording segment; and recording data of the first recording segment that was temporarily recorded in the memory to the storage medium.

Abstract: An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

Abstract: A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the activate allowed logic and the last column counter logic at the beginning of a read or write operation, such as a new command load value, a read count value, and a write count value. In turn, the control logic receives an activate allowed signal from the activate allowed logic, which indicates the times at which a new activate command may be issued. As a result, the memory controller allows an activate command to commence on “even” command cycles or anytime after the last outstanding column command has been issued.

Abstract: Determining a cache hit ratio of a caching device analytically and precisely.

Abstract: A cluster of multiprocessing nodes uses snooping-based cache-coherence to maintain consistency among the cache memories of the multiprocessing nodes. One or more of the multiprocessing nodes each maintain a directory table that includes a list of addresses of data last transferred by cache-to-cache transfer transactions. Thus, upon a local cache miss for requested data, a multiprocessing node searches its directory table for an address of the requested data, and if the address is found in the directory table, the multiprocessing node obtains a copy of the requested data from the last destination of the requested data as indicated in the directory table. Thereafter, a message indicating the completion of a cache-to-cache transfer is broadcast to other connected multiprocessing nodes on a “best efforts” basis in which messages are relayed from multiprocessing node to multiprocessing node using low priority status and/or otherwise unused cycles.

Abstract: An information processing apparatus transmits, by polling, a status verifying message to a disk array apparatus to verify a status of the disk array apparatus. The disk array apparatus attaches, upon receiving the status verifying message, a request for a command of a process to be executed to a response message to the status verifying message, and transmits the response message to the information processing apparatus. The information processing apparatus creates a command based on the request attached to the response message, and transmits the command created to the disk array apparatus.

Abstract: The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

Abstract: With scope-based cache coherence, a cache can maintain scope information for a memory address. The scope information specifies caches in which data of the address is potentially cached, but not necessarily caches in which data of the address is actually cached. Appropriate scope information can be used as snoop filters to reduce unnecessary coherence messages and snoop operations in SMP systems. If a cache maintains scope information of an address, it can potentially avoid sending cache requests to caches outside the scope in case of a cache miss on the address. Scope information can be adjusted dynamically via a scope calibration operation to reflect changing data access patterns. A calibration prediction mechanism can be employed to predict when a scope calibration needs to be invoked.