Abstract: A storage virtualization system is disclosed for performing data migration operations among the virtual LU (logical units) defined by the system. In one aspect of the present invention, the selection of a target virtual LU is based on a policy that makes a recommendation relating to the target virtual LU. The recommendation is based on the I/O activity of the physical devices which constitute the virtual LUs. In another aspect of the present invention, a replacement policy is recommended to replace a current policy. The replacement policy is based on the I/O activity of the physical devices which constitute the virtual LUs.

Abstract: Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.

Abstract: An integrated memory device is proposed. The memory device includes a flash memory having an address parallelism and a data parallelism; the flash memory is partitioned into a plurality of blocks each one including a plurality of sectors, which can be erased individually. A Low Pin Count communication interface is used to receive a command from an external bus, which has a transfer parallelism lower than the address parallelism and the data parallelism; the command includes a selection field for selecting each sector of one or more blocks individually. A control unit then executes an operation corresponding to the command in respect of each selected sector.

Abstract: A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally re-configurable to match the driving and management requirements of the particular memory device. This allows for a limited number of operating system versions to be produced and maintained for a given system by the manufacturer, reducing the possibility of misconfiguration of the system/device by the inadvertent updating or programming of the wrong operating system version by an end user or service personnel. The resulting driver routine and/or operating system is also typically smaller than operating systems/drivers that compile in or load multiple separate drivers into themselves. In one embodiment of the present invention, the software driver is automatically configures itself by querying the memory device for a device ID and/or manufacturer code or by detecting a specific characteristic of the memory device being driven.

Abstract: In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

Abstract: An improved system and method for a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns as a key with various partitioning methods. There may also be a storage policy for specifying how to partition a data table for distributing column chunks across multiple servers and for specifying a level of redundancy for recovery from failure of storage servers.

Abstract: A computer comprising a processor, a volatile main store, a non-volatile random access memory (NVRAM) mirror store, and optionally a cache for the non-volatile mirror store. While programs of the computer are operational, the contents of the volatile main store are mirrored in the non-volatile mirror store such that when a startup signal is received, the contents of the volatile main store are quickly restored from the contents of the non-volatile mirror store.

Abstract: A method of performing a retry in a data storage system, and an apparatus using the same, includes storing information regarding retry parameters corresponding to a position on a storage medium in response to successfully reading data from the position using the retry parameters, reading the data from the position in a subsequent read operation according to the stored information, and rewriting the data at the position.

Abstract: A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is downloaded into the component via the component's JTAG interface. The programmed component then becomes a serial data link between the JTAG port attached to a host programmer and a non-JTAG port attached to the memory device. The circuitry downloaded or programmed into the component controls the timing and the protocol to program the external memory.

Abstract: A system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is stored and retrieved from the general purpose application and file storage device.

Abstract: One embodiment of the present invention can include a method for message and error reporting for multiple extended copy commands that comprises receiving a message from a destination device that is the destination device for at least two concurrent extended copy commands, determining the at least two concurrent extended copy commands that specify the destination device, determining an associated host for each of the at least two extended copy commands and for each of the at least two concurrent extended copy commands, propagating the message to the host associated with that extended copy command.

Abstract: An improved system and method for compression in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Domain specific compression may be applied to a column chunk to reduce storage requirements of column chunks and increase transmission speeds for sending column chunks between storage servers.

Abstract: Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.

Abstract: According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.

Abstract: A method and system for determining the memory utilization of a heap are provided. With the method and system, object allocations and optionally, possible memory freeing events are used to initiate a mark-and-count operation. The mark-and-count operation marks the live objects and maintains a running count of their memory bytes allocated to the live objects, referred to as a live count. The execution of the mark-and-count operation may be dependent upon various criteria including thresholds, functions of the live count, peak live counts, number of memory bytes allocated since a previous mark-and-count operation was performed, and the like. In addition to the live count, a total number of bytes allocated to objects may be maintained in order to obtain information regarding the heap memory utilization.

Abstract: A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.

Abstract: An apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.

Abstract: A system and method is disclosed for the implementation of self-describing configurations in storage array. Each storage drive of the storage array includes at a defined location in the storage drive a self-describing function. When the storage controller receives a request to access a data block in the storage array, the storage controller executes the self-describing function with reference to the requested data block. The result of the executed self-describing function is an identification of the physical location of the data block within the storage array.

Abstract: A buffer random access memory has a first portion reserved for a defect table and a second portion reserved for data caching. A method of managing the buffer random access memory includes determining actual memory space of the first portion which is occupied by the defect table. This identifies unused memory space of the first portion of the buffer random access memory. The method then includes reallocating the unused memory space of the first portion of the buffer random access memory for use in data caching. Controllers and mass storage devices which implement the method are also provided.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.