Patents Examined by Hyung Sough
  • Patent number: 7433904
    Abstract: Various systems and methods for buffer memory management are disclosed. In one embodiment a buffer memory includes at least one queue configured to store a number of buffer access tasks. Buffer reclamation logic is executed to free at least one segment of the buffer memory holding an amount of stale data. Buffer reclamation logic is also included that enables the buffer reclamation logic to submit a buffer access task to the buffer memory based upon a total number of the buffer access tasks stored in the at least one queue.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 7, 2008
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Bruce Burns, Michael Tsukernik, Jamie Mulderig, Joseph Tompkins
  • Patent number: 7430638
    Abstract: To improve caching techniques, so as to realize greater hit rates within available memory, of the present invention utilizes a entropy signature from the compressed data blocks to supply a bias to pre-fetching operations. The method of the present invention for caching data involves detecting a data I/O request, relative to a data object, and then selecting appropriate I/O to cache, wherein said selecting can occur with or without user input, or with or without application or operating system preknowledge. Such selecting may occur dynamically or manually.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: September 30, 2008
    Assignee: Mossman Holdings LLC
    Inventor: John E. Kellar
  • Patent number: 7428622
    Abstract: Systems and methods for managing the distribution of data on a pool of storage media are disclosed. The data are managed based on access patterns, storage media activity, and/or health parameters. An access pattern of one or more units of data in a pool of two or more storage media is determined. At least a portion of the one or more units of data are migrated from one storage medium to another storage medium within the pool of two or more storage media based on the access pattern.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: September 23, 2008
    Inventor: Akhil Tulyani
  • Patent number: 7426621
    Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: September 16, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven J. Kommrusch, Brett A. Tischler
  • Patent number: 7426624
    Abstract: A method for grouping a plurality of storage resources provided by a storage system into storage groups. Storage management software obtains storage resource configuration information set for each of a number of logical partitions in the storage system and groups the storage resources into storage groups such that the storage resource group configuration individually set for the logical partitions in the storage system matches the group configuration of the storage resources constituting the storage groups.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 16, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Fukuguchi, Kyosuke Achiwa, Masafumi Nozawa
  • Patent number: 7424585
    Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices are combined. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group the volumes belonging to the storage system, as a plurality of storage layers 1-3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes to be moved V1 and V2, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: September 9, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Toru Takahashi, Tatsundo Aoshima, Nobuo Beniyama, Takaki Kuroda
  • Patent number: 7424575
    Abstract: In a storage system having a first storage control apparatus and a second storage control apparatus, the first storage control apparatus has: a first memory; a second memory; an input/output control unit for data transfer information in the second memory; and a data transfer control unit having a data buffer and a data transfer register for controlling data transfer between the first memory and second storage control apparatus based on the data transfer information read from the second memory and written in the data transfer register. When a second data transfer is controlled while a first data transfer is controlled, the data transfer control unit writes the first data transfer information and data stored in the data buffer into the second memory, reads the second data transfer information from the second memory and writes the second data transfer information into the data transfer register to control the second data transfer.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 9, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroki Kanai, Shoji Kato, Yuusuke Yauchi
  • Patent number: 7424582
    Abstract: Provided is a storage system having a first storage controller and a second storage controller. An actual device of the second storage controller is mapped to a virtual device of the first storage controller. The first storage controller has a port for transmitting control cylinder information to be written in a control information area of the actual device. As the format data to be transmitted from the first storage controller to the second storage controller, it will suffice so as long as control cylinder information is transmitted, and high speed formatting can be performed since it is not necessary to transmit 0 data.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: September 9, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Takayama, Dai Taninaka, Keishi Tamura
  • Patent number: 7424592
    Abstract: Systems and methods for implementing volume sets in a storage system. According to a first embodiment, a system may include a volume server, a first and a second client computer system, and a plurality of physical block devices. The volume server may be configured to aggregate storage in the plurality of physical block devices into a plurality of logical volumes, wherein a given logical volume includes storage from at least two physical block devices, to distribute a first subset including at least two of the plurality of logical volumes to the first client computer system for input/output as a first volume set configured to be accessed as a single logical device, and to distribute a second subset including at least two of the plurality of logical volumes to the second client computer system for input/output as a second volume set configured to be accessed as a single logical device.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: September 9, 2008
    Assignee: Symantec Operating Corporation
    Inventors: Ronald S. Karr, Randall Ko Shingai, Michael Root
  • Patent number: 7421547
    Abstract: Each storage unit is provided with a table for storing a corresponding unit ID and count value. The controller receives a formatting instruction specifying a first unit ID, and updates the count value on a table corresponding to the first unit ID. The controller receives a write command specifying a second unit ID, acquires a count value corresponding to the second unit ID from the table, and attaches the count value to the data, and writes the data to the storage unit. When a read command specifying the second unit ID is received, the controller reads the data from the storage unit, acquires the count value corresponding to the second unit ID from the table, compares this count value and the count value attached to the read data, sends the read data to the transmission source of the command if these values match, and does not send the data to the transmission source of the command if these values do not match.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: September 2, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Yuko Matsui, Junji Ogawa
  • Patent number: 7418565
    Abstract: A data processing system includes a first storage system including a first host and a first storage subsystem. The first host has access to a first copy manager that is operable to manage a data replication operation. A second storage system includes a second host and a second storage subsystem. The second host has access to a second copy manager that is operable to manage a data replication operation. A first communication link is coupled to the first storage system and the second storage system to exchange management information between the first and second storage systems in order to manage the data replication operation. A data transfer path is configured to transfer data stored in the first storage subsystem to the second storage subsystem and replicate the data of the first storage subsystem in the second storage subsystem. The data transfer path is different from the first communication link.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Takeda, Yoshihiro Asaka, Kenji Yamagami, Katsuyoshi Suzuki, Tetsuya Shirogane
  • Patent number: 7418542
    Abstract: A rewritable, nonvolatile memory includes a first region having stored therein a processing program which allows an electronic device to perform a process, and having a first specific portion which is accessed first upon boot-up by the electronic device; and a second region having stored therein a boot program and a rewrite program. Upon erasing storage contents of the first region, the storage contents of the first region are erased by the rewrite program such that a storage content of the first specific portion is erased last. Upon writing storage contents into the first region, new storage contents are written into the first region by the rewrite program such that a storage content of the first specific portion is written first.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: August 26, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ogo, Shuhji Fujii
  • Patent number: 7418558
    Abstract: A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received externally and reoutputs it in response to an error retry instruction. A broadcast output section broadcasts the memory access request. A broadcast input section receives the broadcast memory access request. A global port holds the received memory access request. A snoop control section transmits and receives cache status information containing a result of snooping, and detects a synchronization error on the basis of the cache status information. If a synchronization error occurs, the snoop control section outputs the error retry instruction to the local port holding the memory access request that resulted in the synchronization error.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventor: Go Sugizaki
  • Patent number: 7415587
    Abstract: When data written into a volume (source volume) in a parity group in a storage apparatus is written into a volume (destination volume) in a parity group in a storage apparatus using a remote copy function, it is determined during the copy whether or not one or both of the following two specified conditions are satisfied for this set of volumes: (1) the performance of the destination volume after a failover is equal to or higher than the performance of the source volume before the failover; and (2) the performance of the destination volume is equal to or higher than the performance of the source volume during the copy. If the condition(s) is not satisfied, the storage apparatus in which the destination volume is defined is changed in configuration to satisfy the condition.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: August 19, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Soejima, Satoshi Miyazaki
  • Patent number: 7415593
    Abstract: A storage control system having no risk of changing the storage content of a logical volume by a data update to a virtual logical volume. A logical volume, which is not correspondent to a virtual logical volume, can be specified when defining a virtual logical volume correspondent to a logical volume. A first storage controller comprises a port capable of connecting to both a logical volume of the first storage controller, and a logical volume of a second storage controller; a virtual logical volume, which is set in association with a logical volume connected to this port; and a virtual logical volume-setting controller for controlling the setting of a virtual logical volume. The virtual logical volume-setting controller is constituted such that the virtual logical volume cannot be set in a logical volume of the first storage controller.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: August 19, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takao Mashima, Dai Taninaka
  • Patent number: 7415578
    Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: August 19, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Shuichi Yagi, Kozue Fujii, Tatsuya Murakami
  • Patent number: 7412563
    Abstract: A method of calculating single and dual parity for a networked array of storage elements is presented. The method includes deriving a first set of n relationships where each of the first set of n relationships consists of an XOR statement equaling zero. Each of the first set of n relationships contains n data symbols from n storage elements and one parity symbol from a first set of parity symbols. The method also includes deriving a second set of n+1 relationships where each of the second set of n+1 relationships consists of an XOR statement equaling zero, containing at least n?1 data symbols from at least n?1 storage elements and one parity symbol from a second set of parity symbols. Using both the first and second sets of derived relationships, scripts are generated to resolve unresolved symbols resulting from possible single- and dual-storage element failure combinations.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: August 12, 2008
    Assignee: Aristos Logic Corporation
    Inventors: Sanjay Subbarao, Kenneth W. Brinkerhoff
  • Patent number: 7412582
    Abstract: A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: August 12, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Kuan-Jui Ho, Hsiu Ming Chu
  • Patent number: 7412569
    Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Abraham Mendelson
  • Patent number: 7412581
    Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology America, Inc.
    Inventors: Toshiyasu Morita, Shumpei Kawasaki