Abstract: A method and apparatus wherein only a partial key is stored in a hashing table is disclosed. By storing a partial key as opposed to storing the entire original key, less data is required to be stored in the hash table. This reduces the attendant memory costs. The reduction in memory requirement does not degrade the hash functionalities whatsoever. Hashing conflicts can be fully resolved by consulting the partial key.

Abstract: An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a code generator that supplies control routines to the microprocessor during at least part of the in-circuit programming operations. The code generator allows the in-circuit programming code to be updated in real time.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: According to exemplary embodiments, there is provided an information storage apparatus having a non-volatile memory device in which a data erase block is larger than a data write block, the apparatus includes an erase device to effect erase in the non-volatile memory device on the basis of a write command from a host, a clean block pointer that stores an address of an erase area in the non-volatile memory device, and information indicative of a position of a write block in the erase area, up to which data is written, a determination device to determine, based on the clean block pointer, whether data associated with the write command is writable in the erase area in the non-volatile memory device, which is erased by the erase device, and a write device to write the data associated with the write command in the erase area, when the determination device determined that the data is writable.

Abstract: Methods and apparatus are provided for managing data in a hierarchal storage subsystem. A plurality of volumes is designated as a storage group for Level 0 storage; a threshold is established for the storage group; space is allocated for a data set to a volume of the storage group; the data set is stored to the volume; the threshold is compared with a total amount of space consumed by all data sets stored to volumes in the storage group. Data sets are migrated from the storage group to a Level 1 storage if the threshold is less than or equal to the total amount of space used by all of the data sets stored to volumes in the storage group. Thus, contention between migration and space allocation is reduced.

Abstract: A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.

Abstract: A disk array system includes a memory that stores first key data inherent to the disk array system, and a disk controller that controls data input/output to/from disk drives. Each of the disk drives includes a disk medium, and an HDD controller, the disk medium having a system area that stores second key data inherent to a disk array system, and a data area that stores user data, the HDD controller controlling data input/output to/from the system area and the data area. The HDD controller, upon a disk drive from among the disk drives being mounted in the disk array system, comparing the first key data and the second key data, and if they do not correspond to each other, operating in an operation mode in which read access from the disk controller to the data area is prohibited.

Abstract: It is an object of the invention to perform memory management for power control appropriately in an information processing apparatus including a non-volatile memory. The information processing apparatus attaches peculiar memory block names to memory blocks allocated in a storage area of the non-volatile memory, respectively, and uses a memory management table for identifying the memory blocks according to the memory block names to perform memory management for the non-volatile memory. When a power supply is turned on again, an application designates a memory block name, whereby the memory block name is searched in the non-volatile memory and data of a memory block corresponding to the memory block name is accessed. Therefore, it is possible to perform memory management for power control appropriately in the information processing apparatus including the non-volatile memory.

Abstract: Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.

Abstract: A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.

Abstract: A lifting and shaping system for a bra is disclosed. The system uses lift platforms shaped to fit into the cups of the bra and formed from thin material such as plastic. The lift platforms are attached to the bra toward the center of the bra. Connectors having one end attached to the lift platform and the other end attached to a slide on the shoulder strap adjust the lift of the lift platform when the slide is moved. Flexible shaping members distribute the lift of the lift platforms and maintain the natural shape of the breasts as they are lifted. Smoothing shields ease the movement of the lift platforms and connectors within the cloth confines of the breast cups. The flexible shaping members may also perform some of the functions of a smoothing shield.

Abstract: The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices coexist. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group arbitrarily each volume belonging to the storage system, as a plurality of storage layers 1-3. For example, storage layer 1 can be defined as a high-reliability layer, storage layer 2, as a low-cost layer, and storage layer 3, as an archive layer. Each storage layer is constituted by a group of volumes corresponding to respective policies (high reliability, low cost, archiving). The user designates volumes V1 and V2 to be moved, in group units, and indicates a storage layer forming a movement destination, whereby the data is relocated.

Abstract: A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.

Abstract: Moving backup data within a storage hierarchy based on a calculated uniqueness of the backup data and on the estimated significance of at least a portion of the backup data. More unique and significant backup data would tend to have higher availability levels. Conversely, less unique and significant backup data would tend to have lower availability levels, or may even cause the backup data to be deleted.

Abstract: A method of controlling a content addressable memory (CAM) device. A data structure is generated that specifies (i) a prioritized set of rules and (ii) storage locations within the CAM device for one or more match clauses of each of the rules. A new rule having a specified priority is recorded in the data structure. Candidate storage locations within the CAM device are identified within the CAM device for the match clauses of each of the rules having a lower priority than the new rule. The candidate storage locations are compared with the storage locations specified by the data structure. Each match clause for which the candidate storage location does not match the specified storage location is stored in the CAM device.

Abstract: Multi-Q FIFO memory devices are configured to support a backed-off standard (BOS) mode of operation. This mode of operation enables automatic re-reading of at least one data word previously read from a first queue in the FIFO memory chip during a first FIFO read operation, in response to a queue-switch back to the first queue during a second FIFO read operation. To support this mode of operation, a read counter associated with the first queue is backed-off at least one entry position in response to the queue-switch.

Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: The present invention is a system and method that performs disk migration in a virtual machine environment. The present invention quickly and easily migrates a virtual machine from one host to another thus improving flexibility and efficiency in a virtual machine environment for “load balancing” systems, performing hardware or software upgrades, handling disaster recovery, and so on. Certain of the embodiments are specifically directed to providing a mechanism for migrating the disk state along with the device and memory states, where the disk data resides in a remotely located storage device that is common to multiple host computer systems in a virtual machine environment. The virtual machine migration process, which includes disk data migration, occurs without the user's awareness and, therefore, without the user's experiencing any noticeable interruption.

Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.