Abstract: A storage apparatus is operable as primary in a remote copy pair and comprises a remote copy component operable to establish a remote copy relationship between said primary and a secondary; a copy component operable at the primary to create a copy for download onto a portable physical storage medium for offline transport to the secondary for upload; a synchronization component for synchronizing data at said secondary with data at said primary using an online link in response to a request for synchronization from the secondary; a metadata component operable to store a dirty state indicator of a portion of a storage space at the primary after establishment of the remote copy relationship at the primary; and the metadata component being operable to limit synchronization at the secondary to the portion of storage having a dirty state indicator at the primary.

Abstract: A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Abstract: A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

Abstract: A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array stores an instruction sequence for execution by the memory device's controller circuit. The sequence can include instructions for testing of the memory device. The execution of the instruction sequence is initiated and the control circuit fetches each instruction from the scratch control array for execution. The results are then reported and/or stored in the scratch control array.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract: A system for minimizing downtime in an appliance-based business continuance architecture is provided. The system includes at least one primary data storage and least one primary host machine. The system includes an intercept agent to intercept primary host machine data requests, and to collect information associated with the intercepted data requests. Moreover, at least one business continuance appliance in communication with the primary host machine and in communication with a remote backup site is provided. The appliance receives information associated with the intercepted data requests from the intercept agent. In addition, a local cache is included within the business continuance appliance. The local cache maintains copies of primary data storage according to the information received. Furthermore, the remote site is provided with the intercepted data requests via the business continuance appliance, wherein the remote site maintains a backup of the primary data storage.

Abstract: A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.

Abstract: Computer systems having a plurality of storage systems could not detect addition of storage systems or configuration changes thereof and automatically redistribute existing volumes based on “hints” provided when the volumes were created. A management computer, which is connected via a network to storage systems having volumes connected via a network to a host computer and which stores data used by the host computer, keeps correspondences between levels indicating specific performances of volumes and storage system characteristics indicating performances of the storage systems. From a first storage system, a level is obtained indicating a performance of a volume of the first storage system allocated to the host computer. The storage system characteristics of the first storage system corresponding to the obtained level indicating the performance of the volume, and storage system characteristics of another storage system are referenced, and the performances of the volumes of the storage systems are compared.

Abstract: A destructive-read memory is one that the process of reading the memory causes the contents of the memory to be destroyed. Such a memory may be used in devices that are intended to acquire data that may have associated usage restrictions, such as an expiration date, usage count limit, or data access fee for the acquired data. Typically, to enforce usage restrictions, and protect against theft, complex and often costly security techniques are applied to acquired data. With destructive-read memory, complex and costly security is not required for stored data. In one embodiment, a write-back mechanism, which may employ security, is responsible for enforcing usage restrictions. If the write-back mechanism determines continued access to acquired data is allowed, then it writes back the data as it is destructively read from the memory.

Abstract: Systems and methods for performing multi-threaded backups and restores. In one embodiment, a log is maintained to record the source of write commands, and the order in which blocks of data are written to a sequential storage device. The source identification of the write command may consist of such identifiers as a protocol dependent Host ID, the extended-copy-specification-defined List ID, a time stamp, and the size of the backup medium block written. The order in which the data is written to the backup medium can be identified with these same Host ID and List ID numbers. When it is desired to restore data corresponding to one of the threads, the desired blocks of data can be identified in the log, and the preceding blocks stored on the backup medium can be skipped.

Abstract: A method comprising receiving a write request; adding the write request to a batch of substantially contiguous disk writes; determining to write the batch of substantially contiguous disk writes to a non-volatile memory; writing the batch of substantially contiguous disk writes to the non-volatile memory; sending a confirmation of writing the batch of substantially contiguous disk writes; receiving a confirmation of the confirmation of writing; and clearing the batch of substantially contiguous disk writes.

Abstract: Computer systems having a plurality of storage systems could not detect addition of storage systems or configuration changes thereof and automatically redistribute existing volumes based on “hints” provided when the volumes were created. A management computer, which is connected via a network to storage systems having volumes connected via a network to a host computer and which stores data used by the host computer, keeps correspondences between levels indicating specific performances of volumes and storage system characteristics indicating performances of the storage systems. From a first storage system, a level is obtained indicating a performance of a volume of the first storage system allocated to the host computer. The storage system characteristics of the first storage system corresponding to the obtained level indicating the performance of the volume, and storage system characteristics of another storage system are referenced, and the performances of the volumes of the storage systems are compared.

Abstract: A system and method for providing online data backup for a computer system. In which the computer system includes an intermediate block data container. The computer system may utilize the intermediate block data container to manage data block release during the online data backup process. When the data storage driver receives a request to write a block into a data area that has already been copied by the backup procedure, then the required write is performed without limitations. If the incoming write request is directed to an area not yet backed-up, then the write process is suspended and the current state of the given data area is copied to the intermediate data storage container. When the copy procedure is completed, the system will allow the write procedure to be executed. Thus, the content of the data block at the moment the backup procedure commenced is stored in the intermediate block container. The content will be copied from the intermediate block data container by the backup procedure when required.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: A disk array system where a plurality of SATA drive enclosures are connected through an FC loop is made capable of continuing to process data even in the event of a fault. When the system is normally operated, a first system controller and a second system controller execute read/write operations from and to disks of a SATA drive enclosure of a disk array via a first interface connector and a second interface connector, respectively, through the FC loop. When an error occurs on a second backend FC loop, the second system controller disconnects itself from the failed second backend FC loop and switches the path to a first backend FC loop which is normally functioning, to access the disk drive.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: A data storage system wherein a data controlling director examines the contents of the tag to determine whether requested read data exists in a local cache memory having this data controlling director or in some other local memory cache, or in a disk drive coupled to this data controlling director; and if the requested read data does exist in the local cache memory having this data controlling director, or in the disk drive coupled to director; the data controlling director sends a copy to the local cache memory of the read request receiving director; updates its tag to show a shared copy will reside in the requesting director's local cache memory; and also sends a message to the read requesting director indicating the data is available for storage in the local cache memory on said one of the plurality of first director/memory boards having the read request receiving director.