Patents Examined by I B Patel
  • Patent number: 7572982
    Abstract: A tap tape of a tape carrier package prevents connection parts from being eroded. The tap tape includes a base film having a device hole formed to mount a driver chip for driving a panel of a flat panel display, input patterns positioned on the base film and having a plurality of electrode pads connected to a side of the device hole, output patterns positioned on the base film and having a plurality of electrode pads connected to the other side of the device hole; and connection parts positioned at the ends of the input patterns or the output patterns and having electrode pads of widths different from widths of the electrode pads.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: August 11, 2009
    Assignee: LG Electronics Inc.
    Inventor: You Se Joon
  • Patent number: 7566833
    Abstract: A wired circuit board that can remove static electricity not only from an insulating base layer and an insulating cover layer but also from a terminal portion, to effectively prevent an electronic component mounted from being damaged by static electricity and also prevent stripping of a semi-conductive layer. In a suspension board with circuit including an insulating base layer formed on a metal supporting board, a conductive pattern formed on the insulating base layer, and an insulating cover layer, formed on the insulating cover layer, to cover the conductive pattern and form an opening, semi-conductive layer is formed in succession on an upper surface of the insulating base layer covered with the insulating cover layer, on a lateral side surface and an upper surface of the conductive pattern, and on a lateral side surface of the insulating base layer adjacent to the metal supporting board.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: July 28, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Yasuhito Funada, Yasunari Ooyabu
  • Patent number: 7563986
    Abstract: One embodiment of a multiple flexible wiring board is a multiple flexible wiring board in which a plurality of flexible wiring boards are configured, and in which a first wiring base material, a first covering film layer, a second wiring base material, a second covering film layer, and an adhesive sheet that bonds the first wiring base material and the second wiring base material such that the first covering film layer and the second covering film layer are opposed, and has opening portions that have been formed corresponding to each of the plurality of flexible wiring boards, are layered. A hollow portion of each of the flexible wiring boards is formed between the first wiring base material and the second wiring base material by the opening portions, and auxiliary opening portions are formed alongside the opening portions.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 21, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hironobu Shitamura
  • Patent number: 7563987
    Abstract: An electronic parts packaging structure of the present invention includes a core substrate having such a structure that a recess portion is provided by forming a prepreg insulating layer having an opening portion therein on a resin layer, and an electronic parts mounted on a bottom portion of the recess portion of the core substrate such that a connection pad of the electronic parts is directed upward, and also, such a structure may be employed that the electronic parts is embedded in a resin layer of a core substrate having a structure that the resin layer is formed on the prepreg insulating layer.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: July 21, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Hiroyuki Kato, Syoji Watanabe
  • Patent number: 7554040
    Abstract: A printed circuit board suitable for dip soldering of component leads in through holes using lead free solder. The printed circuit board includes a plurality of via holes arranged around each through hole in which a component lead is inserted, whereby solder wicking up into the through hole is enhanced and air entrapment is prevented during the dip soldering operation, and heat fatigue resistance of solder joints is improved.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: June 30, 2009
    Assignee: Panasonic EV Energy Co., Ltd.
    Inventors: Yoshitada Nakao, Masateru Tsutsumi, Takayuki Fujikawa
  • Patent number: 7554039
    Abstract: In an electronic device having an interposer substrate as an MCM structure, heat dissipation properties are enhanced while the reliability of joint between the interposer substrate and a motherboard is maintained. In the invention, a metal core base material of great heat capacity and high thermal conductivity is used for both the interposer substrate and the motherboard. Furthermore, a part where a core metal is exposed is provided on at least one of the interposer substrate and the motherboard. A solder joint pad is directly formed on the core metal exposed part, and the interposer substrate is solder-joined to the motherboard.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 30, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Takehide Yokozuka, Masahide Harada, Shiro Yamashita, Kaoru Uchiyama, Shuji Eguchi, Masahiko Asano, Koji Sato
  • Patent number: 7544899
    Abstract: In a printed circuit board on which a first conductor pattern, a second conductor pattern of smaller area than the first conductor pattern and electronic components are mounted, a gap between a first through-hole connected to the first conductor pattern and a first lead pin inserted therein is defined to be larger than that between a second through-hole connected to the second conductor pattern and a second lead pin. With this, it becomes possible to improve solder rise property, without increasing the number of electronic component production processes or degrading strength with respect to the electronic component.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: June 9, 2009
    Assignee: Keihin Corporation
    Inventors: Hiroyuki Kamada, Akira Sato
  • Patent number: 7528327
    Abstract: It is an object to provide an inspection method to enable simple and easy inspection of the electrical connecting state between a connecting terminal of a semiconductor integrated circuit over a substrate such as a glass substrate or a plastic substrate and a crimp connecting terminal of a flexible printed circuit. A crimp inspection terminal is provided to a flexible printed circuit so as to inspect all connecting terminals of the semiconductor integrated circuit over the substrate. A crimp connecting terminal and a crimp inspection terminal are connected with one connecting terminal of the semiconductor integrated circuit by thermocompression. By such a configuration, the inspection of the electrical connecting state between the connecting terminal and the crimp inspection terminal, in the other words, the inspection of conducting state can be performed by using only an external connecting terminal of the flexible printed circuit through the crimp inspection terminal.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 5, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masashi Fujita
  • Patent number: 7522424
    Abstract: A multi-memory media adapter comprised of a first planar element having an upper surface and a lower surface, a second planar element having an upper surface and a lower surface, and formed from a single material. The two planar elements form at least one port, each port capable of receiving one or more types of a memory media card. The adapter has at least one set of contact pins protruding from the lower surface of the first planar element or the upper surface of the second planar element such that the at least one set of contact pins are disposed within the port. The at least one set of contact pins are capable of contacting the contacts of a memory media card inserted into the port. For one embodiment a controller chip is embedded within the single material forming the multi-memory media adapter.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 21, 2009
    Assignee: MCM Portfolio LLC
    Inventors: Sreenath Mambakkan, Venkidu Arockiyaswamy, Larry Lawson Jones
  • Patent number: 7518066
    Abstract: An interface device for coupling an electrical device to a metal junction includes a conformable conductor plate having a first side and a second side. The interface device also includes a plurality of first channels that intersect with a plurality of second channels formed on at least one of the first side and the second side. The formation of the first channels and the second channels weaken the conductor plate. A plurality of protrusions is formed by the intersection of the first channels and the second channels. The protrusions are deformable by coupling the conformable plate between the electrical device and the metal junction. An elongated slot formed throughout at least a portion of the interface device.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: April 14, 2009
    Assignee: GM Global Technology Operations, Inc.
    Inventors: Alex Thompson, Terence G. Ward
  • Patent number: 7507915
    Abstract: A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: March 24, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Chia-Wei Chang, Lin-Yin Wong, Zao-Kuo Lai, Chung-Cheng Lien
  • Patent number: 7501581
    Abstract: A wired circuit board and a producing method thereof are provided which can precisely form an insulating layer and reduce transmission loss with a simple layer structure and also features excellent long-term reliability by preventing the occurrence of an ion migration phenomenon between a ground layer and a positioning mark layer, and the insulating layer to improve the adhesion therebetween and the conductivity of a conductor. A metal supporting board is prepared and a first metal thin film is formed on the metal supporting board. A resist is formed in a pattern and a ground layer and a positioning mark layer are formed on the first metal thin film exposed from the resist at the same time. A second metal thin film is formed over the ground layer and the positioning mark layer, then the resist is removed. An insulating base layer is formed on the first metal thin film including the upper surface of the second metal thin film, thereafter, a conductive pattern is formed on the insulating base layer.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: March 10, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Yasuhito Funada, Jun Ishii
  • Patent number: 7495178
    Abstract: A suspension board with circuit has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and including a terminal portion for connecting to an external terminal, and an antistatic barrier layer formed on the conductive pattern. The antistatic barrier layer includes a metal thin film and a semiconductive layer having at least one end facing the terminal portion and at least the other end in contact with the metal supporting board.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: February 24, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Yasunari Ooyabu
  • Patent number: 7492607
    Abstract: In one aspect, the present invention provides a latch/ejector face plate assembly for an end of an electronics chassis assembly. The face plate is pivotally couplable to a front end of an electronics chassis. The face plate has a latch/ejector that comprises a latching portion that is latchably engageable against a rear side of a latching/fulcrum flange of a electronics rack shelf when the face plate is in a closed position, and an ejector edge that is engageable against a front side of the latching/fulcrum flange when the face plate is in an open position, to thereby provide an ejection force of the electronics chassis.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: February 17, 2009
    Assignee: Lineage Power Corporation
    Inventors: Khanh Nguyen, Gary Kirpatrick
  • Patent number: 7476812
    Abstract: A printed circuit board includes a flexible insulated substrate with a first surface and a second surface at both sides respectively, a wiring layer on the first surface, a reinforcement plate on a part of the second surface and an auxiliary layer between the second surface and the reinforcement plate. A reinforcement edge side of the reinforcement plate is located at the outside of an auxiliary edge side of the auxiliary layer.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: January 13, 2009
    Assignee: Fujikura Ltd.
    Inventors: Kanako Nakajima, Masatoshi Inaba, Yoshiharu Unami
  • Patent number: 7473853
    Abstract: The present invention provides a circuit device capable of controlling deformation of a circuit device while preventing an insulating layer from peeling from a substrate. The circuit device includes a substrate, an insulating layer formed on the substrate, a filler filled into the insulating layer, a conductive layer formed on the insulating layer, and a circuit element formed on the conductive layer, wherein an average particle diameter of the filler filled into the insulating layer is controlled so that a Young's modulus of a part of the insulating layer on a substrate side can be smaller than a Young's modulus of a part of the insulating layer on an opposite side relative to the substrate side.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: January 6, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Murai, Ryosuke Usui
  • Patent number: 7473852
    Abstract: A printed-circuit board and a circuit unit incorporating the circuit board. The printed-circuit board capable of achieving a suitable contact area of sealing resin includes a metal circuit pattern formed on a substrate, a plurality of mounting electrodes formed on the substrate for electrically connecting at least one electronic component, a resist layer of electrically insulating material disposed over the surface of the substrate having openings in the regions corresponding to the plurality of mounting electrodes, and plurality of external connecting terminals provided on edge portions of the substrate for connecting external devices. The resist layer is preferably formed only on the area surrounding the plurality of mounting electrodes inside a sealing region, the sealing region being resin sealed over the surface of the substrate. A circuit unit is also disclosed, including an electronic device and the above-mentioned printed-circuit board.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 6, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Masahiro Higashiguchi, Kunihiro Tan
  • Patent number: 7470865
    Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 ?m thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: December 30, 2008
    Assignee: Hoya Corporation
    Inventors: Takashi Fushie, Takeshi Kagatsume, Shigekazu Matsui
  • Patent number: 7470863
    Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Brian P. Welch
  • Patent number: 7465884
    Abstract: The wired circuit board includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, a semiconductive layer formed on the insulating base layer so as to cover the conductive pattern, and a ground connecting portion formed on the metal supporting board to be in contact with the metal supporting board and the semiconductive layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 16, 2008
    Assignee: Nitto Denko Corporation
    Inventors: Yasunari Ooyabu, Jun Ishii