Patents Examined by I B Patel
  • Patent number: 7253363
    Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: August 7, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Shota Iwasaki, Takehito Inaba
  • Patent number: 7253364
    Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: August 7, 2007
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Sao-Hsia Tang, Shing-Ru Wang
  • Patent number: 7250576
    Abstract: A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: July 31, 2007
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, David L. Edwards, Benjamin V. Fasano, Kamal K. Sikka, Jeffrey A. Zitz, Wei Zou
  • Patent number: 7247800
    Abstract: A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Norio Takahashi
  • Patent number: 7238891
    Abstract: A rigid-flexible circuit board with two rigid areas and one flexible area, with a rigid individual layer which is copper-clad on one side, with an adhesive medium and with a copper foil, the adhesive medium having recesses in the flexible area. The rigid-flexible circuit board can be produced especially easily and economically in that at least in the rigid area there is no flexible individual layer, especially no polyimide film, between the adhesive medium and the copper foil.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: July 3, 2007
    Assignee: Ruwel AG
    Inventor: Roland Muenzberg
  • Patent number: 7238892
    Abstract: Methods and apparatuses for affecting the frequency behavior of connections within a printed circuit board or an integrated circuit are disclosed. Some embodiments include a printed circuit board comprising, a plurality of conductive layers each comprising at least one conductive pad, where each conductive pad on the conductive layers includes a vacancy, and an insulating material disposed about the conductive layers such that the vacancies are at least partially filled with the insulating material.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: July 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Karl J. Bois, David W. Quint, Michael Tsuk
  • Patent number: 7235745
    Abstract: A material for use as part of an internal resistor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. A circuitized substrate adapted for using such a material and resistor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 26, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich
  • Patent number: 7220920
    Abstract: An integrated lead flexure having a slotted coverlay to compensate for curling caused by thermal and hygroscopic-induced expansion and contraction of the coverlay.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 22, 2007
    Assignee: Hutchinson Technology Incorporated
    Inventor: Larry C. Webb, Jr.
  • Patent number: 7214887
    Abstract: A connecting structure includes a circuit board with a first connection land having a plurality of conductor patterns on the surface thereof, a second connection land disposed in a position opposite to the first connection land of the circuit board, and a flexible board including an insulating layer formed so as to surround at least a part of outer periphery of the second connection land. The first connection land and the second connection land are bonded to each other with a bonding member, and the insulating layer is thicker than the total thickness of the second connection land and the first connection land. It is possible to obtain an electronic circuit connecting structure which is free from short-circuit due to running of the bonding member such as solder even with the connecting land greatly reduced in size, and its connecting method.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: May 8, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaaki Higashida, Kenichi Yamamoto, Daisuke Suetsugu, Miyuki Nagaoka, Takashi Imanaka, Toshinari Nitta
  • Patent number: 7205484
    Abstract: A plurality of bonding structures and their forming methods for bonding a FPC to a bonding pad, in particular a bonding pad of a wireless suspension in a head gimbal assembly, using anisotropic conductive adhesive; such structures eliminate the spring-back force in typical anistropic bonding to ensure durable bonding. At the same time, these structures also allow for reworkability under which the bonded parts can be separated easily.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 17, 2007
    Assignee: SAE Magnetics (H.K.), Ltd.
    Inventors: Masashi Shiraishi, Ichiro Yagi
  • Patent number: 7193157
    Abstract: A flexible circuit board is provided to prevent unsuccessful interconnection between the wirings of the flexible circuit board and the output terminals of a semiconductor chip, the flexible circuit board having a plurality of sections of wirings of different sizes, each section including a pattern of wirings of the same size. The flexible circuit board has predetermined patterns of wirings on an insulating material base, and the wirings are electrically connected to the output terminals of a semiconductor chip. A pattern of the wirings of the same size forms a first wiring section, while another pattern of the wirings of the same size form a second wiring section. The flexible circuit board is provided with a pattern transition region between the neighboring wiring sections with wirings of different sizes to avoid unsuccessful interconnection which would be otherwise caused by the difference in size between the wirings.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: March 20, 2007
    Assignee: Tohoku Pioneer Corporation
    Inventors: Atsusi Matsuda, Hidetaka Ohazama
  • Patent number: 7186926
    Abstract: A surface mounting structure for a surface mounting electronic component includes an electronic component, a circuit board and a solder fillet. The electronic component has on a marginal portion thereof a plurality of electrodes, each of which is formed so as to cover at least an under surface, both side faces and an end face of the electronic component. The circuit board has a set of lands, on which the electrodes of the electronic component are joined by soldering. Each land corresponds to one of the electrodes and has a restricting portion, which restricts movement of the electronic component at the time of solder melting during surface mounting, and also has a protrusion on each side of the corresponding electrode. The solder fillet is formed at least on each protrusion so as to correspond to both side faces of the corresponding electrode.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: March 6, 2007
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventor: Kazuhiro Maeno
  • Patent number: 7186921
    Abstract: A circuit device which enables formation of a minute pattern while securing a current capacity and has excellent heat release properties, and a manufacturing method thereof are provided. In a circuit device of the present invention, among multiple wiring layers, a first wiring layer is formed of a thin first conductive pattern and a thick second conductive pattern. Therefore, formation of the minute patterns is realized while securing the current capacity. Moreover, a small-signal circuit element is mounted on the first conductive pattern, and a large-current circuit element is mounted on the second conductive pattern. Thus, circuit elements having different sizes of currents to be handled are mounted on the same board. Furthermore, heat release properties are improved by the second conductive pattern which is formed to be thick.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 6, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki
  • Patent number: 7186923
    Abstract: A printed wiring board comprising conductive layers separated by nonconductive material and having through holes or other nonconductive surfaces on which an electrically conductive carbon coating is formed. The conductive carbon coating includes electrically conductive carbon having a mean particle size not greater than about 1 micron and a water-dispersible organic binding agent. The conductive carbon coating formed on the nonconductive surfaces has a low electrical resistance and is tenacious enough to be plated and exposed to molten solder without creating voids or losing adhesion.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: March 6, 2007
    Assignee: Electrochemicals, Inc.
    Inventors: Charles Edwin Thorn, Frank Polakovic, Charles A. Mosolf
  • Patent number: 7186925
    Abstract: An electronic component having connection terminals on one side thereof is bonded to a circuit board via an adhesive sheet having through-holes. The connection terminals on the electronic component are connected to electrode pads provided on the circuit board via a conductive adhesive in the through-holes. Thus, an electronic circuit device is formed. Using a polymeric resin film sheet for the circuit board and mounting an electronic component, e.g. an LSI, onto the circuit board can provide a small, light, thin, and inexpensive electronic circuit device.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: March 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Norihito Tsukahara, Kazuhiro Nishikawa
  • Patent number: 7183492
    Abstract: A multi-layer printed circuit board having a low noise characteristic, the multi-layer printed circuit board includes: at least one circuit layer; at least one isolation line for dividing the at least one circuit layer into at least two areas, the at least one isolation line forms an open pattern and the at least one isolation line extendedly forms a long neck line into the at least one area, and an internal opening of the long neck line located at a geometric center of the at least one area to improve the isolation, especially for the noises near the resonant frequencies of the isolation areas.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: February 27, 2007
    Assignee: Tatung Co., Ltd.
    Inventors: Shih-Chieh Chao, Chih-Wen Huang, Chun-Lin Liao
  • Patent number: 7183496
    Abstract: An anchoring mechanism and method are provided for securing a component to a printed circuit board. The anchoring mechanism may include a loop, a first leg extending from the loop, and a second leg extending from the loop. The first leg may mount through a first hole of the printed circuit board and include a compressible section to compress when inserted into the first hole and to expand after passing through the first hole. The compressible section of the first leg may support solder between the anchoring mechanism and the first hole. Likewise, the second leg may mount through a second hole of the printed circuit board and include a compressible section to compress when inserted into the second hole and to expand after passing through the second hole. The compressible section of the second leg may support solder between the anchoring mechanism and the second hole.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: George Arrigotti, Tom E. Pearson, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 7180012
    Abstract: A module component with a good shield effect and a low height including a circuit board having mounted thereon a mount device including an electronic part. The device is sealed with a sealing body having a metal film formed on the sealing body surface. A ground pattern is formed at the outer periphery of the principal surface of the circuit board. The metal film is conductively connected with the ground pattern.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: February 20, 2007
    Assignee: Mitsushita Electric Industrial Co., Ltd.
    Inventors: Michiaki Tsuneoka, Koji Hashimoto, Masaaki Hayama, Takeo Yasuho
  • Patent number: 7180005
    Abstract: The printed wiring board includes a substrate, an electrically conductive pattern formed on the substrate, and an electrical insulator covering the substrate and the electrically conductive pattern therewith, wherein a region of the electrically conductive pattern exposed through an opening formed throughout the electrical insulator is used as the pad, and a region except the pad is used as a circuit wire. The opening has opposite ends extending in a first direction beyond the electrically conductive pattern such that opposite ends of the pad in the first direction are defined by the electrically conductive pattern, and further has opposite ends extending in a second direction perpendicular to the first direction to intersect with the electrically conductive pattern such that the pad is defined in shape in the second direction by the opposite ends of the opening extending in the second direction. The pad is smaller in length in the first direction than the circuit wire.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: February 20, 2007
    Assignee: NEC Corporation
    Inventor: Wataru Urano
  • Patent number: 7154045
    Abstract: A wired circuit board having a semi-conducting layer which has excellent chemical resistance, such as acid resistance and alkali resistance, provides no possibility of minute particles being mixed into parts mounted on the wired circuit board; and yet has excellent surface resistivity against electrostatic damage. In the wired circuit board having a conductive layer formed on one side of a base insulating layer in the form of a predetermined wired circuit pattern and a cover insulating layer formed on the conductive layer, a base-side semi-conducting layer and a cover-side semi-conducting layer, which include metal oxide, metal nitride or metal carbide, are formed on the other side of the base insulating layer and the cover insulating layer, respectively, by physical vapor deposition (PVD) or preferably by sputtering.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: December 26, 2006
    Assignee: Nitto Denko Corporation
    Inventors: Yasunari Ooyabu, Takashi Oda, Shinichi Oda