Patents Examined by I B Patel
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Patent number: 7465885Abstract: A circuit carrier is provided. The circuit carrier includes a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.Type: GrantFiled: April 2, 2004Date of Patent: December 16, 2008Assignee: VIA Technologies, Inc.Inventors: Ming-Ren Chi, Wen-Sung Hsu
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Patent number: 7462784Abstract: This invention provides a multilayer printed wiring board which achieves fine pitches. A heat resistant substrate is incorporated in a multilayer printed wiring board and interlayer resin insulation layer and conductive layer are placed alternately on the heat resistant substrate. A built-up wiring board in which respective conductive layers are connected by via hole is formed. A via hole is formed on the surface of a mirror-processed Si substrate by using a heat resistant substrate composed of Si substrate so that finer wiring than a resin substrate having unevenness in its surface can be formed, whereby achieving fine pitches. Further, by forming the wiring on a mirror processed surface, dispersion of wiring decreases thereby decreasing dispersion of impedance.Type: GrantFiled: May 2, 2006Date of Patent: December 9, 2008Assignee: IBIDEN Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
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Patent number: 7462783Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.Type: GrantFiled: August 2, 2004Date of Patent: December 9, 2008Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Navin Kalidas, Paul J. Hundt, Gary P. Morrison
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Patent number: 7446262Abstract: A laminated electronic component includes a ceramic substrate having a first groove provided on a principal surface thereof and extending to the side surfaces, and a resin sheet. The resin sheet includes a thermosetting resin in a semi-cured state and is compression bonded on the principal surface of the ceramic substrate so as to cover the first groove. The resin sheet is then cured by heating. Thus, a combined laminate is produced. When the resin sheet is compression bonded, air trapped in the interface with the ceramic substrate is discharged outside through the first groove. The combined laminate is divided into separate pieces along the first groove. An outer terminal electrode is formed on the outer surface of a resin layer of the resultant separate piece.Type: GrantFiled: January 6, 2005Date of Patent: November 4, 2008Assignee: Murata Manufacturing Co., Ltd.Inventors: Nobuaki Ogawa, Norio Sakai, Yoshihiko Nishizawa
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Patent number: 7439450Abstract: The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.Type: GrantFiled: June 6, 2006Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventor: Mark S. Johnson
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Patent number: 7435913Abstract: Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.Type: GrantFiled: June 26, 2006Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventors: Chin Hui Chong, Choon Kuan Lee
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Patent number: 7432451Abstract: An electro-optical device including an electro-optical panel, a flexible base member connected to the electro-optical panel, and an electronic component mounted on the flexible base member. The electronic component having conductive terminals electrically connected to a plurality of terminals disposed on the flexible base member, the plurality of terminals are disposed on one surface of the flexible base member, and the conductive terminals and the plurality of terminals two-dimensionally overlap each other. The flexible base member has first wires which are connected to the plurality of terminals and disposed on the one surface, hole portions formed in the flexible base member to correspond to at least one terminal, and second wires connected to the at least one terminal through connection members disposed in the hole portions and disposed on the other surface of the flexible base member opposite to the one surface.Type: GrantFiled: January 24, 2006Date of Patent: October 7, 2008Assignee: Seiko Epson CorporationInventor: Kazuyuki Yamada
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Patent number: 7427719Abstract: An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.Type: GrantFiled: March 21, 2006Date of Patent: September 23, 2008Assignee: Intel CorporationInventors: Tao Liang, Stephen H. Hall, Howard Heck, Gary A. Brist, Bryce Horine
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Patent number: 7420822Abstract: A power distribution module for a personal recreational vehicle includes a housing and a cover. The housing defines an interior and includes a wall having an array of receptacle openings. The receptacle openings are adapted to receive and secure electrical components inside the housing. A distribution harness includes a plurality of electrical conductors and is coupled to the housing wherein the electrical conductors are in electrical communication with the electrical components inside the housing. The power distribution module can optionally include a decal to assist quick and accurate placement of the electrical components during the manufacturing process. A method for producing a personal recreational vehicle having a standardized housing over a range of models. The housing includes a component arrangement guide for locating and installing electrical components.Type: GrantFiled: June 28, 2006Date of Patent: September 2, 2008Assignee: Arctic Cat Inc.Inventor: Darrel Janisch
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Patent number: 7417195Abstract: A printed circuit board 2 and an FPC board 3 to be connected together are each given a multilayer structure wherein insulating films 23, 33 and interconnection patterns 22, 32 are stacked alternately. In the FPC board 3, connecting signal lines are distributed among the multilayered interconnection patterns 22, and in the printed circuit board 2, interconnecting to lands 32a formed on a connection face thereof is carried out using interconnection patterns 32 of inner layers. By this means, it is possible to greatly increase the number of connecting signal lines between the printed circuit board 2 and the FPC board 3.Type: GrantFiled: February 3, 2004Date of Patent: August 26, 2008Assignee: DENSO CorporationInventors: Makoto Totani, Toshihiro Miyake, Fumio Kojima
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Patent number: 7417196Abstract: A chip-type electronic component built-in multilayer board includes a multilayer board including two or more layered dielectric layers and an inner conductor pattern, and a chip-type electronic component which is provided at the interface of the upper and lower dielectric layers and includes an external terminal electrode. The external terminal electrode is connected to an in-plane conductor provided at a interface via a first connection conductor extending along the chip-type electronic component in the lower direction from the interface of the upper and lower dielectric layers, and a second connection conductor extending along the chip-type electronic component in the upper direction from the interface of the upper and lower dielectric layers.Type: GrantFiled: March 9, 2007Date of Patent: August 26, 2008Assignee: Murata Manufacturing Co., Ltd.Inventors: Ryuichiro Wada, Tetsuya Ikeda
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Patent number: 7405366Abstract: An interposer 2 including a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further including: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: GrantFiled: January 26, 2006Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7405363Abstract: A first high speed transmission line board (1) having a stripline structure is composed of a first elastomer sheet (1A) that has a fixed dielectric constant, plural first elastomer strips (1B) that are conductive, arrayed at two edges of the first elastomer sheet (1A), and plural first high speed transmission lines (1C) formed in a pattern connecting two ends of the first elastomer strips (1B). A first surface layer board (2) is composed of a second elastomer sheet (2A) that is nonconductive, and plural second elastomer strips (2B) that are conductive, arrayed similarly to the first elastomer strips (1B), at two edges of the second elastomer sheet (2A). A multilayer board is configured by laminating the first surface layer board (2) on the first high speed transmission line board (1), and external connecting terminals are in pressurized contact with the plural second elastomer strips (2B), so that the plural first high speed transmission lines (1C) are connected.Type: GrantFiled: September 28, 2004Date of Patent: July 29, 2008Assignee: J.S.T. Mfg. Co., Ltd.Inventor: Shuichi Inoue
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Patent number: 7402894Abstract: The present invention relates to an integrated circuit carrier. The integrated circuit carrier includes a receiving plate to which an integrated circuit can be mounted and a plurality of electrical connection islands surrounding the receiving plate. A plurality of resilient interconnection arms is also provided which each interconnect either: adjacent electrical connection islands, or an electrical connection island and the receiving plate.Type: GrantFiled: May 30, 2006Date of Patent: July 22, 2008Assignee: Silverbrook Research Pty LtdInventor: Kia Silverbrook
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Patent number: 7394024Abstract: An oxide superconductor current lead in which generation of Joule heat at joint portions with a system side conductor and a power supply side conductor is reduced with use of an oxide superconductor with less heat penetration into a super conducting equipment system is provided.Type: GrantFiled: February 5, 2004Date of Patent: July 1, 2008Assignees: Dowa Mining Co., Ltd., Chubu Electric Power Co., Inc.Inventors: Shuichi Kohayashi, Kazuyuki Uemura, Shigeo Nagaya, Naoji Kashima
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Patent number: 7388157Abstract: A printed wiring board is made of first and second substrates superimposed on each other. The first and second substrates respectively include a core layer made of resin containing carbon fibers. The second substrate has the outline different from that of the first substrate. A stepped surface is defined on the front surface at least of the first substrate. Electrodes can be formed on the stepped surface as well as on the back surface of the first substrate and the front surface of the second substrate. This structure enables detection of an electric signal from the stepped surface. A further flexibility can thus be achieved in locating electrodes as compared with a conventional printed wiring board having uniform substrates simply superimposed on each other. This results in an expanded use or purpose for a printed wiring board.Type: GrantFiled: December 30, 2005Date of Patent: June 17, 2008Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani, Kenichiro Abe, Kenji Iida
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Patent number: 7385144Abstract: A method and apparatus is provided for forming a printed circuit board or other panel in which an array of vias are arranged in a desired connection grid within one or more layers of the board and then the board and vias are cut to form an edge of the board where a surface of the vias is exposed. The board may be orthogonally mounted on its edge to another thin circuit board or aperture sheet with the exposed surface of each via directly connected to such other board or sheet.Type: GrantFiled: November 17, 2005Date of Patent: June 10, 2008Assignee: Harris CorporationInventors: Ronald J. Hash, Mitchell Percival
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Patent number: 7381901Abstract: A hinge board having a hinge bending part and a rigid part includes: not less than two flexible wiring boards including a polyimide sheet layer, a conductor layer having a circuit formed on both sides or one side of the polyimide sheet layer, and a coverlay film layer covering the conductor layer; and a bonding material for bonding the flexible wiring boards. At least one of the flexible wiring boards is a flexible double-sided wiring board including the conductor layers on both sides of the polyimide sheet layer. Moreover, the flexible wiring boards are bonded to each other in the rigid part by use of the bonding material in such a manner that a space part is formed between the flexible wiring boards in the hinge bending part.Type: GrantFiled: October 19, 2005Date of Patent: June 3, 2008Assignee: Nippon Steel Chemical Co., Ltd.Inventors: Takashi Tanaka, Hidenori Nakajima, Yuichi Tokuda
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Patent number: 7378602Abstract: A multilayer core board 10 includes tapered first via hole conductors 51 extending from the outer surface of a first insulating layer 24 to conductive portions 42a of a power source layer 42, second via hole conductors 52 extending from the outer surface of a second insulating layer 26 to the conductive portions 42a of the power source layer 42, tapered third via hole conductors 53 extending form the outer surface of the second insulating layer 26 to conductive portions 40a of a ground layer 40, and fourth via hole conductors 54 extending from the outer surface of a center insulating layer 22 to the conductive portions 40a of the ground layer 40. The first via hole conductors 51 are tapered, and thus the interval distance to the adjacent first via hole conductor 51 is shorter than straight-shaped first via hole conductors, and thus the pitch of the first via hole conductor 51 at the positive pole side and the fourth via hole conductor 54 at the negative pole side can be sufficiently reduced.Type: GrantFiled: October 11, 2005Date of Patent: May 27, 2008Assignee: Ibiden Co., Ltd.Inventor: Tomoyuki Ikeda
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Patent number: 7378596Abstract: A flex-rigid wiring board has an insulative adhesive interposed between portions, lapping over each other, of the rigid and flexible substrates; and the interconnecting electrode pads on the rigid and flexible substrates are electrically connected to each other through a conductor lump penetrating the insulative adhesive, thereby providing lowered inductance in the high-frequency band, shortened signal-delay time, reduced noise generation due to signal reflected-wave, reduced drop impact, high connection reliability and high freedom of wire connection, and the wiring board can advantageously be manufactured with a reduced cost and a high yield.Type: GrantFiled: April 16, 2004Date of Patent: May 27, 2008Assignee: Ibiden Co., Ltd.Inventors: Katsuo Kawaguchi, Hirofumi Futamura