Patents Examined by I B Patel
  • Patent number: 7102463
    Abstract: This invention relates to semiconductor devices and to printed circuit boards (PCB) or circuit assemblies used to electrically connect components. Delay devices are associated with the conductive traces or with integrated circuits. Delay is used to offset then realign the wave edges of propagating signals so as to minimize electric field effects on nearby signals. Impedance controlling devices are used to minimize reflections. The effects of split planes may be minimized or negated.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: September 5, 2006
    Assignee: Cytek Corporation
    Inventor: Clifford Clark
  • Patent number: 7060911
    Abstract: A conductor strip includes a first end portion soldered to a printed circuit board, and a second end portion welded to a rechargeable battery. The conductor strip also includes a connecting portion disposed between the first and the second end portions. The connecting portion has a smaller width than that of the first end portion so that the peeling force acting on the first end portion is alleviated.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: June 13, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Naoya Tanaka
  • Patent number: 7019223
    Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 6972381
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device includes: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: December 6, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6921869
    Abstract: A conductive pattern made of copper foil is formed on a base material in each of a plurality of laminated flexible printed circuit boards, and a land is formed to expose the conductive pattern at a predetermined position in the base material. The plurality of flexible printed circuit boards are laminated to adjust each land, and the conductive pattern of each flexible printed circuit board is connected through the each land.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: July 26, 2005
    Assignee: Fujikura Ltd.
    Inventors: Ichiro Terunuma, Kazuya Akashi, Atsushi Momota
  • Patent number: 6916995
    Abstract: A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: July 12, 2005
    Assignee: Broadcom Corporation
    Inventors: Kevin L. Seaman, Vernon M. Wnek
  • Patent number: 6900393
    Abstract: A solder bearing—bearing wafer (100) is provided which is used to connect a first electronic device to a second electronic device. The wafer includes a substrate body having a first surface and second surface, opposing the first surface. The first surface has grooves (115, 117) formed therein and includes length of solder (130) dispersed within groove. Upon heating the solder and placement of the wafer between the first and second devices, the two devices are connected.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: May 31, 2005
    Assignee: Teka Interconnections Systems, Inc.
    Inventors: Joseph S. Cachina, James R. Zanolli
  • Patent number: 6879465
    Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: April 12, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tatsumi Tsuchiya, Yuhsuke Matsumoto, Takaaki Murokawa, Naoki Fujii, Takuya Satoh, Yasuhiro Mita, Hiroyasu Tsuchida, Yoshio Uematsu
  • Patent number: 6878884
    Abstract: An electronic device is mounted on a wiring board, which includes: a substrate having through holes, and lands extending on surfaces of the substrate and adjacent to openings of the through holes. Further, at least one coating layer is provided, which coats at least one part of an outer peripheral region of the at least one land, in order to cause that the at least one part is separated from a lead-less solder, thereby preventing any peel of the land from the surface of the substrate.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 12, 2005
    Assignee: NEC Corporation
    Inventor: Yuki Momokawa
  • Patent number: 6875930
    Abstract: A multilayered substrate includes a plurality of connection point groups, each including connection points. At least two inside conductors are each electrically coupled to inside connection points in at least two connection point groups, wherein each of the inside conductors is substantially equal in length between the inside connection points of adjacent connection point groups which is defined as a inside conductor length. At least two outside conductors are each electrically coupled to outside connection points in at least two connection point groups, wherein each of the outside conductors is substantially equal in length between the outside connection points of the adjacent connection point groups which is defined as an outside conductor length. The inside conductor length is shorter than the outside conductor length.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: April 5, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Melvin Peterson
  • Patent number: 6872894
    Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: March 29, 2005
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
  • Patent number: 6867375
    Abstract: In order to provide a flexible oxide superconducting cable which is reduced in AC loss, tape-shaped superconducting wires covered with a stabilizing metal are wound on a flexible former. The superconducting wires are preferably laid on the former at a bending strain of not more than 0.2%. In laying on the former, a number of tape-shaped superconducting wires are laid on a core member in a side-by-side manner, to form a first layer. A prescribed number of tape-shaped superconducting wires are laid on top of the first layer in a side-by-side manner, to form a second layer. The former may be made of a metal, plastic, reinforced plastic, polymer, or a composite and provides flexibility to the superconducting wires and the cable formed therewith.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: March 15, 2005
    Assignee: Southwire Company
    Inventors: Raburn L. Hughey, Uday K. Sinha, David S. Reece, Albert C. Muller
  • Patent number: 6861591
    Abstract: A printed circuit board having an insulating board and a plurality of wiring patterns formed over the insulating board by screen printing and provided with first conductive pattern bent parts and wiring parts linked to the first conductive pattern bent parts. A pattern width in the first conductive pattern bent parts is greater than that of the patterns of those of the wiring parts positioned close to and on both sides of the first conductive pattern bent parts.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: March 1, 2005
    Inventor: Akihiro Kusaka
  • Patent number: 6858807
    Abstract: A substrate is adapted to accommodate a circuit configuration. The novel substrate is stable under alternating loads and it favorably dissipates heat. To this end, the substrate has a fastening zone to be connected to a contact element that is to be provided. The fastening zone is fixed on the carrier substrate with a first section. A second section projects from the plane of the carrier substrate, and the first and the second sections are adapted to be electrically and mechanically connected to the contact element.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: February 22, 2005
    Assignee: EUPEC Europaeische Gesellschaft fuer Leistungshalbleiter mbH
    Inventors: Gottfried Ferber, Reimund Pelmer
  • Patent number: 6852932
    Abstract: A multi-layer circuit board having apertures that are selectively and electrically isolated from electrically grounded member and further having selectively formed air bridges and/or crossover members which are structurally supported by a polymeric material. Each of the apertures selectively receives an electrically conductive material.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: February 8, 2005
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Achyuta Achari, Andrew Zachary Glovatsky, Robert Edward Belke, Brenda Joyce Nation, Delin Li, Lakhi N. Goenka, Mohan R. Paruchuri, Robert Joseph Gordon, Thomas Bernd Krautheim
  • Patent number: 6849806
    Abstract: An electrical apparatus having resistance to atmospheric effects includes at least one electrical device and a packaging structure. The packaging structure substantially encloses the at least one electrical device. The packaging structure includes a corrosion-resisting agent.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: February 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Patent number: 6846993
    Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 25, 2005
    Assignee: NEC Corporation
    Inventor: Isao Matsui
  • Patent number: 6844504
    Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: January 18, 2005
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Alan E. Wang, Kevin C. Olson, Thomas H. Di Stefano
  • Patent number: 6844505
    Abstract: A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: January 18, 2005
    Assignee: NCR Corporation
    Inventors: Jun Fan, James L. Knighten, Arthur R. Alexander, Norman W. Smith
  • Patent number: 6841738
    Abstract: A flexible rigid printed wiring board includes a plurality of rigid wiring boards having wiring patterns. The rigid wiring boards are spatially separate from each other. The flexible rigid printed wiring board also includes a flexible portion. The flexible portion connects the rigid wiring boards, and includes an insulating and flexible resin sheet. The insulating and flexible resin sheet includes first portions of first and second sub resin sheets. The first portions of the first and second sub resin sheets are bonded together. The first and second sub resin sheets have second portions covering and adhering to surfaces of the rigid wiring boards.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: January 11, 2005
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Shigeru Michiwaki, Shinji Suga, Mitsuru Otsuki