Abstract: A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) formed on a substrate and connected to a backside metal line of a backside power distribution network (BSPDN). The semiconductor device also includes a lateral junction diode co-integrated with the stacked nanosheet FET.

Abstract: A display device includes: a substrate with a plurality of pixels on the substrate, the plurality of pixels including light emitting areas; a plurality of transistors in each of the plurality of pixels on the substrate; an overcoating layer on the plurality of transistors; a plurality of first electrodes on the overcoating layer in the plurality of pixels, the plurality of first electrodes connected to each of the plurality of transistors; a bank between the plurality of pixels on the overcoating layer; a light emitting part disposed on the plurality of first electrodes and the bank; and a second electrode disposed on the light emitting part, wherein the overcoating layer includes a concave part between the light emitting areas of the plurality of pixels.

Abstract: A circuit includes an electrostatic discharge protection circuit disposed along a major surface of a substrate, an internal circuit also disposed along the major surface but laterally spaced from the electrostatic discharge protection circuit, and a coupling capacitor operatively coupled and physically disposed between the electrostatic discharge protection circuit and the internal circuit. The coupling capacitor includes a first metal element formed in a first one of a plurality of metallization layers disposed over the major surface, and a second metal element also formed in the first metallization layer. A number of the metallization layers vertically disposed between the first metallization layer and the major surface is equal to or less than 1.

Abstract: A display device includes a support plate including a first area and a second area changed depending on a switch of an operation mode, and a display panel including first and second display areas respectively overlapping first and second areas. The second display area includes a first partial area including a pixel circuit of a first group, a pixel circuit of a second group, and a first light emitting device electrically connected to the pixel circuit of the first group or the pixel circuit of the second group, and second partial areas each including a second light emitting device electrically connected to the pixel circuit of the first group or the pixel circuit of the second group. The pixel circuit of the second group includes a first partial circuit and a second partial circuit, with a corresponding second partial area among the second partial areas therebetween.

Abstract: A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.

Abstract: A display device includes: a substrate having an emission area and a non-emission area; an insulating layer covering a circuit element on the substrate, the insulating layer including a contact part exposing a portion of the circuit element; a conductive pattern on the insulating layer and electrically connected to the circuit element through the contact part; a first electrode on the insulating layer and integrally formed with the conductive pattern; a pixel defining layer over the first electrode, the pixel defining layer including an opening exposing a portion of the first electrode; a light emitting layer on the first electrode; and a second electrode on the light emitting layer, wherein the conductive pattern and the first electrode include a first layer, a second layer, and a third layer, which are sequentially stacked on one surface of the insulating layer, and wherein the second layer includes an aluminum-nickel-lanthanum-based alloy.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer. The second semiconductor region includes: a first portion; a second portion located on the first portion and having a higher second-conductivity-type impurity concentration than the first portion; and a third portion positioned between the second portion and the gate electrode and having a higher concentration of a first element than the second portion. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.

Abstract: An electronic device including a substrate, a first insulating layer, a semiconductor layer, a second insulating layer and a data line is provided. The first insulation layer is disposed on the substrate. The semiconductor layer is disposed on the first insulating layer. The second insulating layer is disposed on the semiconductor layer and has a first hole. The data line is disposed on the substrate, and the data line is electrically connected to the semiconductor layer through the first hole. Corresponding to an edge of the semiconductor layer, the first insulating layer has a recess.

Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

Abstract: A semiconductor device includes a non-volatile memory structure. A layout of metallization layers in the semiconductor device coupled with the non-volatile memory structure is configured to achieve a low likelihood of electromigration in the non-volatile memory structure, particularly at operating temperature parameters associated with demanding applications such as automotive and/or industrial, among other examples. The non-volatile memory structure is electrically coupled with a first metallization layer. The first metallization layer electrically couples the non-volatile memory structure with a second metallization layer that is configured as a write bit line metallization layer for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure with a third metallization layer above the second metallization layer. The third metallization layer is configured as a read bit line metallization layer for the non-volatile memory structure.

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Abstract: A semiconductor package may include a first redistribution layer structure, a chiplet structure on the first redistribution layer structure, a plurality of first connection members on the first redistribution layer structure, a first molding material on the first redistribution layer structure and molding the chiplet structure and the plurality of first connection members, and a second redistribution layer structure on the first molding material. The chiplet structure may include a third redistribution layer structure, a first chiplet and a second chiplet on the third redistribution layer structure, and a bridge die on a bottom surface of the third redistribution layer structure.

Abstract: Disclosed systems and techniques are directed to correct an out-of-plane deformation (OPD) of a substrate. The techniques include obtaining, using optical inspection data, a profile of the out-of-plane deformation of the substrate and identifying, using the obtained profile, one or more parameters characterizing a saddle-shaped stress of the substrate. The techniques further include computing, using the one or more identified parameters, one or more characteristics of a stress-compensation layer (SCL) for the substrate and causing the SCL to be deposited on the substrate. The techniques further include causing a stress-mitigation beam to be applied to a plurality of edge regions of the SCL, wherein settings of the stress-mitigation beam are determined using the one or more identified parameters.

Abstract: An image sensor including a pixel array in which a plurality of pixels are arranged, and a nano-condensing lens array including a plurality of condensing areas respectively corresponding to the plurality of pixels. Each of the plurality of condensing areas includes at least one nanostructure that condenses light on a corresponding pixel among the plurality of pixels, and the at least one nanostructure is arranged in each of the plurality of condensing areas such that a condensing capability of the at least one nanostructure included in each of the plurality of condensing areas varies according to a distance from a center of the nano-condensing lens array to each of the plurality of condensing areas.

Abstract: Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.

Abstract: A display device includes: a substrate including a display area, a pad area spaced apart from the display area in a first direction, and a bending area disposed between the display area and the pad area, a transfer line overlapping the pad area and extending from pad area in a direction opposite to the first direction, a connection line disposed on the transfer line, connected to the transfer line, and overlapping the bending area, an organic insulating layer disposed on the connection line and entirely overlapping the connection line, and an inorganic insulating layer disposed on the organic insulating layer, defining an opening overlapping the organic insulating layer, and overlapping one end of the organic insulating layer.

Abstract: A memory device includes a stacked structure, a first conductive type doping layer, a second conductive type doping layer, a first conductive plug and a second conductive plug. The stacked structure is located above the substrate, and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. A projection area of the first conductive type doping layer is larger than a projection area of the stacked structure. The second conductive type doping layer surrounds the first conductive type doping layer and forms a hetero-junction with the first conductive type doping layer. The first conductive plug is electrically connected to the first conductive type doping layer. The second conductive plug is electrically connected to the second conductive type doping layer. The memory device may be a 3D AND flash memory.

Abstract: In one example, an apparatus includes a substrate, an array of memory cells on the substrate, and an array of pixels over the array of memory cells. The array of memory cells is in a grid pattern. The array of pixels is in a diamond pattern that is oriented at an angle relative to the grid pattern of the array of memory cells. Each pixel of the array of pixels overlaps respective portions of at least two memory cells of the array of memory cells. Each pixel of the array of pixels is electrically connected to an output of a respective memory cell of the array of memory cells.

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, the first semiconductor chip including first through-vias, first bump structures on the first front surface of the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including second through-vias, adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, and an encapsulant between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips. The adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.