Abstract: Embodiments of a flexible electroluminescent (FEE) device are described. An FEE device includes a device stack with a quantum dot (QD) film configured to generate a first light having a first peak wavelength and a flexible substrate configured to support the device stack and emit a first portion of the first light. The FEE device further includes an encapsulation layer disposed on the device stack and an outcoupling layer disposed on the flexible substrate. The encapsulation layer can be configured to provide mechanical and environmental protection to the FEE device from moisture or oxygen. The outcoupling layer can be configured to prevent total internal reflection of a second portion of the first light within the flexible substrate and extract the second portion from the flexible substrate.

Abstract: A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

Abstract: To eliminate influence caused by a difference in coefficient of linear expansion between a substrate and another material, and to secure a stable mounting structure of a semiconductor element. A semiconductor device includes a glass substrate and the semiconductor element. The glass substrate includes a through hole that penetrates front and back surfaces. Furthermore, the glass substrate includes a stepped portion on an outer periphery of the through hole. The semiconductor element is joined to the stepped portion of the glass substrate. For example, in a case where an imaging element is used as the semiconductor element, image quality of an image obtained by imaging is improved by preventing defocus of light incident on the imaging element.

Abstract: Disclosed are an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and an organic light-emitting diode (OLED), a photoelectric conversion layer and a light-filtering layer which are on the base substrate, wherein the OLED and the light-filtering layer both are on a side, distal from the base substrate, of the photoelectric conversion layer, an orthographic projection of the photoelectric conversion layer on the base substrate is at least partially overlapped with an orthographic projection of the light-filtering layer on the base substrate, the orthographic projection of the photoelectric conversion layer on the base substrate is outside an orthographic projection of the OLED on the base substrate, the light-filtering layer is light transmittable, and a transmittance of the light-filtering layer to light in a target band is smaller than or equal to a transmittance thresholds.

Abstract: Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written). As a result, even in the case of displaying a still image, stable operation is easily performed. In addition, an operation interval of a driver circuit can be extended, which results in a reduction in power consumption of a display device. Moreover, a light-storing material is used in a pixel portion of a self-luminous display device to store light, whereby the display device can be used in a dark place for a long time.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a magnetoresistive random access memory (MRAM) cell with a memory array landing pad contacting a first bottom metal level contact and an MRAM pillar electrically connected to the memory array landing pad. The semiconductor structure may also include a logic interconnect contacting a second bottom metal level contact and a dielectric cap above the MRAM cell and the logic interconnect. The MRAM cell and logic interconnect may be electrically connected to a top metal level through the dielectric cap.

Abstract: A semiconductor device includes a semiconductor element having a substrate, a drift layer, a base region, a source region, trench gate structures, an interlayer insulating film, a source electrode, and a drain electrode. The substrate is made of silicon carbide. The drift layer is disposed on the substrate and has an impurity concentration lower than the substrate. The base region is made of silicon carbide and disposed on the drift layer. The source region is made of silicon carbide having an impurity concentration higher than the drift layer. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The interlayer insulating film covers the gate electrode and the gate insulating film. The source electrode is in ohmic-contact with the source region. The drain electrode is disposed on a rear surface of the substrate.

Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.

Abstract: Provided is a display module including: a substrate including a mounting surface on which a plurality of inorganic light emitting diodes (LEDs) are mounted, a side surface, and a rear surface disposed opposite to the mounting surface; a front cover bonded to and covering the mounting surface; a metal plate bonded to the rear surface; and a side cover configured to surround the side surface, wherein the front cover extends to an area outside of the mounting surface in a first direction in which the mounting surface extends, and wherein the side cover is provided to extend, in a second direction in which the mounting surface faces, from an upper side of the metal plate to a lower end of a region of the front cover to seal the side surface from an outside.

Abstract: A method for manufacturing a display panel (10), the display panel (10), and a display apparatus (20) are provided. The method includes the following. A first substrate (110) and a second substrate (120) are provided, where the first substrate (110) includes a growth substrate (111), an epitaxial structure (112), and a first metal layer (113) that are sequentially stacked, and the second substrate (120) includes a circuit substrate (121) and a second metal layer (122) stacked on the circuit substrate (121). An activation treatment is performed on the first metal layer (113) and the second metal layer (122). The first metal layer (113) and the second metal layer (122) are bonded after the activation treatment, to cause the growth substrate (111), the epitaxial structure (112), the first metal layer (113), the second metal layer (122), and the circuit substrate (121) sequentially stacked. The growth substrate (111) is lift off.

Abstract: An ohmic contact includes a first semiconductor layer a second semiconductor layer, and a heterointerface between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer has a two-dimensional electron sheet region in which a two-dimensional electron sheet is formed. The ohmic contact further includes a metal terminal covering the first semiconductor layer and filling a plurality of direct access pathways that provide direct lateral contact with the two-dimensional electron sheet region. The semiconductor device is fabricated by providing the semiconductor layers, etching the direct access pathways, and depositing metal material to fill the direct access pathways and cover the semiconductor layers.

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

Abstract: A method of manufacturing a display device includes providing an inorganic layer on a carrier substrate, providing a first flexible substrate on the inorganic layer, providing a first shielding layer including a metal on the first flexible substrate, providing a first barrier layer on the first shielding layer, and providing a thin film transistor layer on the first barrier layer. The inorganic layer includes at least one material selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy), and a thickness of the inorganic layer is in a range from about 10 ? to about 6000 ?.

Abstract: An ohmic contact includes a first semiconductor layer a second semiconductor layer, and a heterointerface between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer has a two-dimensional electron sheet region in which a two-dimensional electron sheet is formed. The ohmic contact further includes a metal terminal covering the first semiconductor layer and filling a plurality of direct access pathways that provide direct lateral contact with the two-dimensional electron sheet region. The semiconductor device is fabricated by providing the semiconductor layers, etching the direct access pathways, and depositing metal material to fill the direct access pathways and cover the semiconductor layers.

Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.