Patents Examined by J. M. Davis
  • Patent number: 4056408
    Abstract: A method of reducing the switching time of certain semiconductor devices and particularly gain-operated semiconductor devices. The depth of maximum defect generation in a given type of semiconductor devices having a block PN junction is determined on irradiation with a given radiation source emitting particles with molecular weight of at least one (1), preferably protons or alpha particles; and the energy level of the radiation source adjusted to provide the depth of maximum defect generation adjacent a blocking PN junction of the type of semiconductor device. At least one semiconductor device of said given type of semiconductor device is positioned with a major surface thereof to be exposed to the adjusted radiation source, and thereafter irradiated with the adjusted radiation source to a given dosage level to reduce the switching time of the semiconductor device.
    Type: Grant
    Filed: March 17, 1976
    Date of Patent: November 1, 1977
    Assignee: Westinghouse Electric Corporation
    Inventors: John Bartko, Kuan H. Sun
  • Patent number: 4050966
    Abstract: A method for preparing semiconductor components from silicon as the base material. The components have at least two zones, produced by diffusion, with different conduction type. The diffusion of the individual zones takes place from dopant containing nickel layers applied at the semiconductor crystal surface. The nickel layer including the dopant contained therein, is applied by chemical means.
    Type: Grant
    Filed: June 19, 1975
    Date of Patent: September 27, 1977
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Wolfle, Dieter Rucker, Uta Lauerer
  • Patent number: 4045258
    Abstract: A method of producing a semiconductor arrangement comprises diffusing through a diffusion mask into a semiconductor body a semiconductor region of a first type of conductivity and applying to the semiconductor body a semiconductor region of a second type of conductivity extending to the surface of the semiconductor body at least partially in a region which is caused by the diffusion mask when diffusing the region of the first type of conductivity.
    Type: Grant
    Filed: January 31, 1975
    Date of Patent: August 30, 1977
    Assignee: Licentia Patent-Verwaltungs-GmbH
    Inventor: Reinhold Kaiser
  • Patent number: 4043836
    Abstract: Disclosed is a method of manufacturing semiconductor devices including a step of irradiating the devices to alter the turnoff and forward drop characteristics thereof. The irradiation is carried out at a temperature above 100.degree. C, and preferably in the range of 150.degree. to 375.degree. C. No post irradiation annealing step is required.
    Type: Grant
    Filed: May 3, 1976
    Date of Patent: August 23, 1977
    Assignee: General Electric Company
    Inventor: Yen Sheng Edmund Sun
  • Patent number: 4043848
    Abstract: An insulated gate field effect transistor having a self-aligned gate, reduced capacitance, and lower surface step heights is fabricated with the use of a silicon nitride layer which serves first as a diffusion mask, than as an oxidation barrier, and ultimately as a gate dielectric. In an alternate embodiment, lower threshold voltages are achieved by replacing the initial gate dielectric with a thinner dielectric having a reduced surface state density.
    Type: Grant
    Filed: June 23, 1972
    Date of Patent: August 23, 1977
    Assignee: Texas Instruments Incorporated
    Inventor: Bernard Bazin
  • Patent number: 4038110
    Abstract: An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist.
    Type: Grant
    Filed: June 14, 1976
    Date of Patent: July 26, 1977
    Assignee: IBM Corporation
    Inventor: Bai-Cwo Feng
  • Patent number: 4035198
    Abstract: A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: July 12, 1977
    Assignee: International Business Machines Corporation
    Inventors: Robert Heath Dennard, Vincent Leo Rideout
  • Patent number: 4030942
    Abstract: The disclosure teaches the use of aluminum nitride as a mask for utilization of ion implantation in the formation of semiconductor configurations as well as an underlying material for use in semiconductor lift-off techniques in device formation and the deposition of metallization contact lines and interconnections.
    Type: Grant
    Filed: October 28, 1975
    Date of Patent: June 21, 1977
    Assignee: International Business Machines Corporation
    Inventors: William Andrew Keenan, Charles Thomas Kroll
  • Patent number: 4030943
    Abstract: The specification describes new high frequency ion implanted semiconductor devices, novel microwave integrated circuits employing same, and a planar fabrication process for both wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor substrate. Next, a heavily doped buried region is ion implanted through an opening in the mask and into the substrate to a preselected controlled depth. Thereafter, one or more additional ion implants are made through the mask opening to complete the active device regions and a PN junction therebetween, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor substrate.
    Type: Grant
    Filed: May 21, 1976
    Date of Patent: June 21, 1977
    Assignee: Hughes Aircraft Company
    Inventors: Don H. Lee, Kenneth P. Weller, William F. Thrower
  • Patent number: 4030948
    Abstract: A copolymer which is the reaction product of a tetracarboxylic acid dianhydride, and organic diamine and a di(aminoalkyl) poly siloxane where the di(aminoalkyl) poly siloxane constitutes 18 - 45 mole percent of the total amine requirement of the polymer and is applicable as a conformal protective coating for electronic devices.
    Type: Grant
    Filed: July 21, 1975
    Date of Patent: June 21, 1977
    Inventor: Abe Berger
  • Patent number: 4029527
    Abstract: The "emitter-dip effect" is eliminated by applying a layer of an undoped polycrystalline semiconductor onto the surface of a select zone to be doped in a semiconductor body, for example, such as on the emitter zone of a silicon body and then diffusing a select dopant through the undoped polycrystalline semiconductor layer into the select zone of the semiconductor body.
    Type: Grant
    Filed: June 18, 1975
    Date of Patent: June 14, 1977
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andreas Glasl, Helmuth Murrmann
  • Patent number: 4028150
    Abstract: A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.
    Type: Grant
    Filed: February 9, 1976
    Date of Patent: June 7, 1977
    Assignee: IBM Corporation
    Inventors: Robert Henry Collins, Richard F. Levine, William D. North, Gerald D. O'Rourke, Gerald R. Parker
  • Patent number: 4026736
    Abstract: This disclosure is directed to an integrated semiconductor structure with combined dielectric and PN junction isolation including the fabrication method therefor wherein a compensating P type channel is formed adjacent to the dielectric side isolation across one end portion of the electrically isolated N type collector region as well as around the bottom portion of the dielectric side isolation material or layer in order to overcome the N channel inversion (in P type semiconductor material) that is formed when the dielectric isolation material is silicon dioxide. The disclosed structure is an NPN transistor device having a buried sub-collector region of N+ type conductivity and further includes a P type substrate thereby providing a PN junction isolating substrate. The silicon dioxide material or layer is used to electrically isolate the side portions of the NPN transistor device from adjacent devices.
    Type: Grant
    Filed: July 18, 1975
    Date of Patent: May 31, 1977
    Assignee: Motorola, Inc.
    Inventor: Israel Arnold Lesk
  • Patent number: 4025364
    Abstract: A process for simultaneously fabricating epitaxial resistors, base resistors, and vertical transistor bases in a semiconductor substrate utilizes the stopping power of different layers of materials to determine the location of impurity concentrations induced by ion implantation.
    Type: Grant
    Filed: August 11, 1975
    Date of Patent: May 24, 1977
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Peter R. Smith
  • Patent number: 4021270
    Abstract: A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide/nitride layer is stripped away and a second oxide/nitride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide/nitride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other.
    Type: Grant
    Filed: June 28, 1976
    Date of Patent: May 3, 1977
    Assignee: Motorola, Inc.
    Inventors: Merrill Roe Hunt, Christopher Angelos Ladas, Sal Thomas Mastroianni
  • Patent number: 4016006
    Abstract: In a method of heat-treating a number of wafers each of which consists of a substance of poor heat conduction and a semiconductor layer formed on one surface of the substance, a method of heat treatment of wafers characterized in that the heat treatment is carried out under the state under which an auxiliary wafer made of a substance of good heat conduction is held in proximity to the other surface of the substance of poor heat conduction, whereby the wafers for the heat treatment are prevented from being cracked and have the characteristics made uniform.
    Type: Grant
    Filed: March 16, 1976
    Date of Patent: April 5, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yoshinaka, Takaaki Aoshima, Yoshimitsu Sugita
  • Patent number: 4016017
    Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions.
    Type: Grant
    Filed: November 28, 1975
    Date of Patent: April 5, 1977
    Assignee: International Business Machines Corporation
    Inventors: Joseph Adam Aboaf, Robert Wallace Broadie, William Aaron Pliskin
  • Patent number: 4014714
    Abstract: A combination insulating means comprised of a pn-junction overlaid with a SiO.sub.2 filling within a groove is provided between IC elements in a monolithic semiconductor device. Such combination insulating means electrically and mechanically isolate at least two areas of a n-conductive surface zone, each of which supports an IC element. The n-conductive surface zone is supported on a p-conductive silicon base and the free surface of the n-conductive surface zone is coated with a Si.sub.3 N.sub.4 layer, which during the various fabrication steps of the monolithic semiconductor device protects coated areas of the n-conductive surface zone from etchants, oxidation and from dopants.
    Type: Grant
    Filed: August 1, 1975
    Date of Patent: March 29, 1977
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmuth Murrmann, Ulrich Schwabe
  • Patent number: 4013484
    Abstract: A process for fabricating high density, high voltage CMOS devices. The process provides self-aligning, full channel stops which are formed prior to the fabrication of the active devices. The aligned full channel stops and a well are formed in the substrate without intermediate masking.
    Type: Grant
    Filed: February 25, 1976
    Date of Patent: March 22, 1977
    Assignee: Intel Corporation
    Inventors: Edward J. Boleky, Charles Scott
  • Patent number: 4013485
    Abstract: The electrical properties of MIS semiconductor devices, which have been damaged by radiation, are restored by treating the devices in a properly oriented RF field at low pressure.
    Type: Grant
    Filed: April 29, 1976
    Date of Patent: March 22, 1977
    Assignee: International Business Machines Corporation
    Inventors: Tso-Ping Ma, William Hsioh-Lien Ma