Abstract: In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300.degree. C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600.degree. - 900.degree.

Abstract: Portions of a polycrystalline silicon layer disposed on an insulator are removed after diffusing donor impurities into and through the regions to be removed. The regions to be retained are either previously or simultaneously doped with acceptor impurities. The method provides improved control of the size and the shape of the edges of the retained regions.

Abstract: An improved memory device to be used in a D.C. circuit which device includes a pair of spaced electrodes between which extends a body of a generally amorphous high resistance memory semiconductor material made of a composition of at least two elements and wherein the application to the electrodes of one or more set voltage pulses in excess of a given threshold level produces a relatively low resistance filamentous path comprising a deposit of at least one of said elements in a crystalline or relatively ordered state. When one or more D.C. current reset pulses of a given value and duration are fed through the filamentous path, the crystalline deposit is returned to a relatively disordered state and the more electropositive element of said composition normally tends to migrate to the negative electrode and the more electronegative element thereof normally tends to migrate to the positive electrode.

Abstract: A lateral transistor or the like is made by the steps of forming a first insulating layer on a semiconductor substrate and providing a first hole in this insulating layer so as to expose a first surface portion of the substrate. An impurity of a first conductivity type is introduced through the hole and a second hole is formed in the insulating layer so as to expose a second surface portion of the substrate spaced apart from the first portion. Then, a second insulating layer of a material different from that of the first layer is formed on the first insulating layer and on the first and second surface portions of the substrate. Subsequently, third and fourth holes are formed in the second insulating layer within the confines of these holes to expose at least portions of the first and second surface portions of the substrate. Then, an impurity of a second conductivity type is introduced into the exposed first and second surface portions of the substrate through the third and fourth holes.

Abstract: An integrated circuit structure with full dielectric isolation, i.e., the electrical isolation is provided by electrically insulative material, is formed by ion bombarding a silicon substrate with ions such as nitrogen, oxygen or carbon to implant subsurface region containing such ions and heating the resulted bombarded substrate to a temperature sufficient to react the introduced ions with the substrate to form a subsurface layer which has a different etchability than silicon. An epitaxial layer of monocrystalline silicon is then deposited on the substrate, after which a pattern of regions of electrically insulating material is formed extending through the epitaxial layer beyond the substrate surface into contact with the subsurface layer to laterally surround a plurality of pockets in said silicon. An electrically insulative layer is formed on the surface of the epitaxial layer continuous with the electrically insulating lateral regions.

Abstract: A method of making a semiconductor device is described in which a selected surface portion of a silicon wafer is masked against oxidation, and then the surface is oxidized to grow a thermal oxide which sinks into the silicon surface at the unmasked areas, with the result that the masked silicon remains as a mesa surrounded by the sunken oxide. Then semiconductor devices can be provided by various techniques in the silicon mesa. The advantages include the provision of flat junctions, as distinguished from dish junctions in the prior art, reduced capacitance resulting from the extension of the device interconnections over the silicon wafer, and a flatter surface on top of the wafer reducing the risk of damage to the deposited interconnections.

Abstract: A method for manufacturing a power transistor having a highly doped emitter zone and a narrow base zone with a flat doping profile.In a long-term diffusion step ensuring the flat doping profile, the base zone is diffused into a lowly doped substrate serving as a collector. In a subsequent etching process, the base zone is etched down to a shell-shaped remainder. A large area, highly doped emitter zone with a steep doping profile and thus a high emitter efficiency is introduced into this shell-shaped remainder in a short-term diffusion step.

Abstract: An improved method for the manufacture of semiconductor devices which shortens the processing steps leading to metallization is disclosed. The present invention utilizes a controlled silicon etch process which allows emitters to be diffused into both the emitter and base sites. Undesired emitters are then removed from the base sites prior to metallization which enables the semiconductor devices to be manufactured in fewer numbers of steps than that required by the prior art processing techniques. The invented method for forming a contactual region in a semiconductor substrate having a planar base region comprising the steps of forming at least one opening through an insulating layer on the substrate. Next, an impurity is diffused into the substrate through the opening to form a base region. A passivating layer is then disposed over the insulating layer and the opening. A pattern is etched through the passivating layer so as to expose a selected area in the base region of the substrate.

Abstract: A metal-oxide-semiconductor (MOS) transistor structure includes gate, source and drain regions. Said structure also includes a gate electrode electrically connected and contiguous to either the source region or the drain region. Typically, the gate electrode is formed of a conductive material through which impurity diffusions may pass substantially unimpeded.

Abstract: A semiconductor layer, such as an epitaxial layer on a suitable substrate is subjected to controlled bombardment by neutrons whereby the atoms of the semiconductor layer are converted via nuclear reaction into doping material atoms.

Abstract: A silicon substrate is selectively implanted with ions and heated in a oxidizing atmosphere. Thus an oxide film is formed on the substrate so that portions of the film formed on regions implanted with the ions is partly embedded in the substrate. Then the film is etched until the surface of the substrate is selectively exposed. An impurity is diffused into the exposed surface portions to form base regions in the substrate after which the process as above described is repeated to form windows for emitter diffusion and electrodes. Also silicon is epitaxially grown on a silicon substrate selectively provided with SiO.sub.2 films so that silicon in the form of a single crystal is grown on the exposed surface portions of the substrate while polycrystalline silicon grown on the SiO.sub.2 films. The above process is repeated to convert the polycrystalline silicon to silicon dioxide for separating the silicon regions on the exposed surface portions from one another.

Abstract: The surface of a semiconductor substrate, such as a silicon crystal, is uniformly coated with a layer of Si.sub.3 N.sub.4 and at least two selectively spaced windows are provided therein. The uncovered silicon surface within such windows is then coated with a layer of SiO.sub.2. Next, a SiO.sub.2 area within a first window along with a portion of the adjacent Si.sub.3 N.sub.4 areas are coated with a photo-lacquer mask while the substrate surface area beneath the second window is doped with a select dopant. This procedure is then reversed and the Photo-lacquer mask is removed from the first window and applied onto the second window while the substrate surface area beneath the first window is contacted with select dopant to produce a doped zone. In this manner, considerable tolerance for positioning of a diffusion mask is provided.

Abstract: A method of manufacturing semiconductor devices is provided which comprises the steps of depositing a coating of platinum on the surface of a silicon substrate prior to the formation of a plated nickel layer thereon, plating a layer of nickel on the silicon substrate coated with platinum, and then subjecting the structure to the process of heat treatment to thereby cause the platinum to diffuse into the silicon substrate, whereby the platinum acts to increase the adhesion strength of the plated nickel layer on the silicon substrate and further the platinum element diffused into the silicon substrate serves as a lifetime killer of carriers to thereby improve the switching characteristic of the semiconductor device.

Abstract: An IMPATT diode is manufactured by doping a silicon n-type epitaxial layer and bombarding the doped layer with ions, preferably protons.

Abstract: A method of ion implantation, in which boron ions are generated by introducing a boron-oxide containing material vapor into a conventional gas discharge ion generation source.

Abstract: An improved insulated gate field effect transistor is achieved by using a material such as silicon nitride as an ion implantation and oxidation mask overlying a channel region, forming source and drain regions or extensions thereof by implanting ions of a conductivity modifier into a semiconductor substrate, and subjecting the implanted ions to a drive-in diffusion whereby the conductivity modifier ions are redistributed. The ion implantation allows greater control over the amount of conductivity modifier implanted in the lightly doped source and drain regions, the more uniform distribution of conductivity modifier increases the source-drain breakdown voltage, while the use of the silicon nitride mask provides simultaneously for general alignment of the channel region with the effective gate length.

Abstract: A semiconductor material is doped or alloyed under vacuum with an impurity by thermal decomposition and by sedimentation resulting from centrifugal force. The doping material is alternatively applied by evaporation before being subjected to centrifugal force and may be heated up to the melting point before completion of the centrifugal action. A centrifuge is provided having a thermal insulating layer between the outer wall of a rotor and a support for basic semiconductor material to be doped. The doping impurity material to be evaporated onto the basic solid state material is placed in the center of the centrifuge rotor.

Abstract: Low impurity concentration planar anode regions are formed without a mask in a plurality of cathode regions which are isolated from each other on their lateral edge by an insulating barrier and connected to each other by a low resistivity polycrystalline body. Metal contacts to the anode regions and the common cathode polycrystalline body are coplanar.

Abstract: A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in nonblooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

Abstract: This disclosure relates to a self-aligned photoresist process for use in removing silicon dioxide from the tops of silicon mesas or other semiconductor mesa structures. The specific application is in the production of an array of mesa P-N diodes on a semiconductor slice which have oxide passivation in the valleys between the mesas. In the production of such diodes, an early step in the overall processing of the devices is to thermally oxidize the entire mesa structure prior to diffusing the P-N junction therein. In order to prepare the slice for the junction diffusion, it is necessary to first remove the thermal oxide from only the tops of the mesas leaving the oxide in the valleys for the purpose of isolation. This oxide removal is provided herein without complicated alignment steps by depositing a photoresist over the oxide passivation layer in such a way that the photoresist thickness over the mesas is thinner than it is in the valleys between the mesas.