Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component and a superconductor component arranged over the semiconductor component. The superconductor component comprises a continuous portion of a superconductor material and a discontinuous portion of a non-ferromagnetic metal. The discontinuous portion is configured to increase the critical field of the superconductor component. It has been found that providing a superconductor component with a discontinuous portion of non-ferromagnetic metal may increase the critical field of the superconductor component, allowing the device to be operated in a stronger magnetic field. Further aspects provide a method of fabricating the device, and the use of a non-ferromagnetic metal to increase the critical field of a superconductor component of a semiconductor-superconductor hybrid device.

Abstract: A semiconductor element separated from an original substrate includes: an element substrate; and an element constitution part formed on the element substrate, wherein a pattern indicating a position of the semiconductor element before separating the semiconductor element from the original substrate is formed on at least one of the element substrate and the element constitution part.

Abstract: An array substrate and a manufacturing method thereof, and a display panel are provided. A first thin film transistor includes a first electrode, a second electrode, a first active pattern, and a first gate electrode. The first active pattern extends in a thickness direction of the array substrate. The first gate extends in the thickness direction of the array substrate. At least two of first sidewalls of the first electrode of the first thin film transistor and at least two second sidewalls of the second electrode of the first thin film transistor are disposed surround a first opening which penetrating the first thin film transistor.

Abstract: Provided is a semiconductor device having a dual gate field-effect transistor and a sensor in electrical communication with the transistor. The field-effect transistor can have a first gate electrode, a second gate electrode, a source electrode, a drain electrode, a semiconductor layer with parts in contact with the source and drain electrodes, a bi-layer gate insulator, and a second gate insulator. The bi-layer gate insulator can include a first layer and a second layer, the first layer located between the second layer and a first side of the semiconductor layer, the second layer located between the first layer and the first gate electrode. The second gate insulator can be located between the second gate electrode and a second side of the semiconductor layer, and the sensor can be in electrical communication with the second gate electrode.

Abstract: A semiconductor structure for measuring a breakdown voltage of a pn-junction, said semiconductor structure comprises: a substrate; a sensor device comprising an optical active region comprising said pn-junction in said substrate, wherein said sensor device is configured to apply a reverse bias voltage to said pn-junction; and an emitter located adjacent to said optical active region in said substrate and configured to provide charge carriers to said optical active region in order to trigger breakdown of said pn-junction when said reverse bias voltage is equal to or greater than said breakdown voltage.

Abstract: A wafer processing device may include a wafer exchanger including two or more blades, each of the two or more blades may be configured to receive a wafer, the two or more blades may be rotatable about an axis on a single horizontal plane, and the two or more blades may be movable between at least a load cup and a robot access location; wherein the load cup may include a wafer station that is vertically moveable relative a blade located in the load cup and may be configured to remove a wafer from a blade located in the load cup and place a wafer on a blade located in the load cup. Other devices, load cups and methods are also disclosed herein.

Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.

Abstract: A method for manufacturing a film on a support having a non-flat surface comprises: providing a donor substrate having a non-flat surface, forming an embrittlement zone in the donor substrate so as to delimit the film to be transferred, forming the support by deposition on the non-flat surface of the film to be transferred, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the support.

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: A method of fabricating a magnetoresistive device may comprise forming an electrically conductive region and forming a first seed region on one side of the electrically conductive region. A surface of the first seed region may be treated by exposing the surface to a gas. A second seed region may be formed on the treated surface of the first seed region. The method may also comprise forming a magnetically fixed region on one side of the second seed region.

Abstract: The present invention relates to a process for irradiating a processed surface (5) of a processed substrate (1) so as to obtain a predefined temperature profile, the processed surface (5) comprising a first area (11) and a second area (13), said first area (11) having a first combination of optical properties and thermal properties, and said second area (13) having a second combination of optical properties and thermal properties, said first combination and second combination being different. A further object of the invention is a system (21) for irradiating a processed surface (5) of a processed substrate (1) so as to obtain a predefined temperature profile, the processed surface (5) comprising a first area (11) and a second area (13), said first area (11) having a first combination of optical properties and thermal properties, and said second area (13) having a second combination of optical properties and thermal properties, said first combination and second combination being different.

Abstract: An interconnect structure includes first, second, and third insulating layers, first, second, and third conductive lines, and first, second, third, and fourth conductive vias. The first conductive line is embedded in the first insulating layer. The second conductive line is embedded in the second insulating layer and comprises a first portion, a second portion, and a third portion. The third conductive line is embedded in the third insulating layer. The first and second conductive via are embedded in the first insulating layer. The third and fourth conductive via are embedded in the second insulating layer. A first cross-sectional area surrounded by the first conductive line, the first conductive via, the second conductive via, the first portion, and the second portion is substantially equal to a second cross-sectional area surrounded by the first portion, the third portion, the third conductive via, the fourth conductive via, and the third conductive line.

Abstract: A display module and a fabrication method thereof, and a display device, and relates to the field of display technologies, to synchronously implement a display function and a surface tactile reproduction function. The display module includes: a base substrate, a plurality of piezoelectric structures positioned on a first side of the base substrate, and at least one isolation portion positioned on the first side of the base substrate and configured to separate any two adjacent piezoelectric structures. A pixel hole is arranged in at least one of three positions, i.e., a position of the piezoelectric structure, a position of the isolation portion, and a position between the piezoelectric structure and the isolation portion. The display module also includes a plurality of pixel structures, and each of the plurality of pixel structures is positioned in one of the pixel holes.

Abstract: A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.

Abstract: A substrate processing apparatus includes a processing unit configured to perform a preset processing on a substrate; a transfer unit, including a holder configured to hold the substrate, configured to carry the substrate into/from the processing unit by displacing the holder which holds the substrate; and a substrate inspection unit configured to acquire, at an outside of the processing unit, information indicating a surface state of the substrate held by the holder.

Abstract: This application relates to an apparatus and method for processing a wafer. In an embodiment of this application, an apparatus for processing a wafer includes: a heater including a pedestal, where a top portion of the pedestal includes an annular edge step and a wafer pocket recessed relative to the annular edge step to accommodate a wafer; a side ring, including an outer portion and a top portion, where the outer portion surrounds an outer side wall of the pedestal, and the top portion covers an outer portion of the annular edge step and includes a centripetal slant bevel; and a shadow ring, a bottom portion thereof including a slant bevel matching the centripetal slant bevel of the top portion of the side ring.

Abstract: The embodiment provides a graphene-containing membrane producible by wet-coating and excellent in electric properties, a process for producing the membrane, a graphene-containing membrane laminate, and a photoelectric conversion device using the graphene-containing membrane. The graphene-containing membrane contains graphene having a graphene skeleton combined with polyalkylenimine chains. The membrane has a ratio of the photoelectron intensity at the energy peak position of C1s orbital to that at the bonding energy on an X-ray photoelectron spectrum measured on an ITO film of 288 eV in a range of 5.5 to 20. This membrane can be produced by heating a graphene oxide-containing film in the presence of polyalkyleneimine and further heating the film in the presence of a reducing agent. The graphene-containing membrane can be so installed in a photoelectric conversion device that it is placed between the photoelectric conversion layer and the electrode.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including checking a leak from a process furnace before a substrate is processed. The checking includes: (a) measuring, by a partial pressure sensor provided at an exhaust pipe, an oxygen partial pressure value of a residual oxygen after the process furnace is vacuum-exhausted; (b) comparing the oxygen partial pressure value measured by the partial pressure sensor with a threshold value; and (c) when the oxygen partial pressure value is higher than the threshold value in (b), performing at least one among: purging the process furnace and evacuating the process furnace.