Patents Examined by Jae Lee
  • Patent number: 11916066
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: February 27, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Simone RascunĂ¡
  • Patent number: 11915978
    Abstract: A first regrowth layer and a second regrowth layer comprising GaAs having high resistance are regrown on a surface of an etching stop layer exposed to the bottom of a first groove and a second groove, and then n-type InGaAs is regrown on the first regrowth layer and the second regrowth layer, whereby a source region and a drain region configured to make contact with a channel layer are formed in the first groove and the second groove respectively.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 27, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takuya Hoshi, Yuki Yoshiya, Hiroki Sugiyama, Hideaki Matsuzaki
  • Patent number: 11908868
    Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhisa Nagao, Noriaki Kawamoto
  • Patent number: 11901394
    Abstract: The present application discloses a display panel and a manufacturing method therefor, and the method includes steps of: forming a photosensitive element layer, forming a light collimating layer on the photosensitive element layer, and forming an active light-emitting matrix layer on the light collimating layer; where the step of forming the light collimating layer includes: providing a metal substrate, putting the metal substrate into an electrolyte, and preparing a porous oxidized metal as the light collimating layer by a two-step oxidation method.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 13, 2024
    Assignees: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: En-Tsung Cho, Jie Ding, Je-Hao Hsu, Lidan Ye
  • Patent number: 11886064
    Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 30, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dewei Song, Fei Ai
  • Patent number: 11871648
    Abstract: This application relates to preparation of organic photomultiplication photodetectors, and more particularly to an organic photomultiplication photodetector with bi-directional bias response and a method for producing the same. The photodetector includes an anode layer, an anode modification layer, an interfacial modification layer, an active layer and a cathode layer arranged in sequence. The interfacial modification layer is made of Al2O3. The anode layer is made of indium tin oxide (ITO). The anode modification layer is made of poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)(PEDOT:PSS). The active layer is made of poly(3-hexylthiophene-2,5-diyl):[6,6]-phenyl-C70-butyric acid methyl ester (P3HT:PC70BM). The cathode layer is made of aluminum, silver or gold.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiyuan University of Technology
    Inventors: Linlin Shi, Yanxia Cui, Guohui Li, Ye Zhang, Wenyan Wang, Ting Ji
  • Patent number: 11864400
    Abstract: Provided are an organic light-emitting device and an electronic apparatus including the same. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, wherein the emission layer includes a first host and a first dopant, and the first host and the first dopant each satisfy Equations 1-1 and 1-2. In Equations 1-1 and 1-2, T1(H1)onset, T1(D1)onset, T1(H1)max, and T1(D1)max are understood by referring to the description provided herein. T1(H1)onset?T1(D1)onset??Equation 1-1 T1(H1)max?T1(D1)max.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: January 2, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seokgyu Yoon, Hyosup Shin, Hyojeong Kim
  • Patent number: 11854794
    Abstract: A method for cleaning a through via including the following steps is provided: heating a cleaning fluid to a predetermined temperature; mixing the cleaning liquid with an inert gas and entering into a cleaning cavity; atomizing the cleaning liquid in an atomizer to spray on a wafer surface and to wet an inner wall and a bottom of the through via; and closing a cleaning liquid valve.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 26, 2023
    Assignee: NATIONAL CENTER FOR ADVANCED PACKAGING CO., LTD.
    Inventors: Daping Yao, Liqiang Cao
  • Patent number: 11849639
    Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 19, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Sergei Vyatcheslavovich Gronin, Flavio Griggio, Raymond Leonard Kallaher, Noah Seth Clay, Michael James Manfra
  • Patent number: 11848221
    Abstract: A method includes disposing, by using a transport module of a workpiece storage system, a first workpiece on a first workpiece carrier; disposing, by using the transport module, the first workpiece carrier with the first workpiece in a workpiece container; disposing, by using the transport module, a second workpiece in the workpiece container, wherein the first workpiece and the second workpiece have different sizes; and transferring, by using the transport module, the workpiece container containing the second workpiece and the first workpiece carrier with the first workpiece to a stocker to store the workpiece container.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Chi Chiu, Jen-Ti Wang, Ting-Wei Wang, Kuo-Fong Chuang
  • Patent number: 11843018
    Abstract: An imaging device includes a first photoelectric conversion region (170) receiving light within a first range of wavelengths, a second photoelectric conversion region (170) receiving light within a second range of wavelengths, and a third photoelectric conversion region (170) receiving light within a third range of wavelengths. At least a portion of a light-receiving surface of the first photoelectric conversion region has a first concave-convex structure (113), and a light-receiving surface of the second photoelectric conversion region has a different structure (111) than the first concave-convex structure.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 12, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Sozo Yokogawa
  • Patent number: 11842907
    Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 12, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shu-Kwan Danny Lau, Toshiyuki Nakagawa, Zhiyuan Ye
  • Patent number: 11837669
    Abstract: A dynamic photodiode may comprise a substrate comprising a first surface opposite a second surface, the substrate being of a first doping type; a substrate region disposed on the first surface, the substrate region comprising a substrate contact configured to be grounded; a first doped region disposed on the first surface, the first doped region being of the first doping type and comprising a first contact configured to receive a first voltage; a second doped region disposed on the first surface, the second doped region being of a second doping type opposite to the first doping type and comprising a second contact configured to receive a second voltage. The substrate region may surround the second doped region, the second doped region may surround the first doped region, and exposed portions of the substrate form light absorbing regions may be configured to generate electron-hole pairs in the substrate.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 5, 2023
    Assignee: ActLight SA
    Inventors: Denis Sallin, Maxim Gureev, Serguei Okhonin
  • Patent number: 11825720
    Abstract: A display panel a display device are provided. The display panel includes a plurality of pixel units arranged in a row direction and in a column direction, the display panel includes a display region. An edge of the display region includes a fold line formed by connecting a line segment extending in the row direction and a line segment extending in the column direction, a parallelogram region formed in the display region taking two adjacent line segments as adjacent sides includes the pixel units; directions from an intersection point of the two adjacent line segments to end points of the two adjacent line segments other than those at the intersection point are a first direction and a second direction, respectively; in the parallelogram region, aperture ratios of the pixel units arranged in at least one of the first direction and the second direction increase gradually.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: November 21, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yin Deng, Bo Wu, Xiaojing Qi
  • Patent number: 11818905
    Abstract: Provided are an organic light-emitting device and an electronic apparatus including the same. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, wherein the emission layer includes a first host and a first dopant, and the first host and the first dopant each satisfy Equations 1-1 and 1-2. In Equations 1-1 and 1-2, T1(H1)onset, T1(D1)onset, T1(H1)max, and T1(D1)max are understood by referring to the description provided herein. T1(H1)onset?T1(D1)onset??Equation 1-1 T1(H1)max?T1(D1)max.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 14, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seokgyu Yoon, Hyosup Shin, Hyojeong Kim
  • Patent number: 11810804
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: November 7, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Patent number: 11812600
    Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Charles C. Kuo, Abhishek A. Sharma, Van H. Le, Jack Kavalieros
  • Patent number: 11800812
    Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Patent number: 11798824
    Abstract: The present invention is related to a heating device for heating an object material using a laser beam, the heating device comprising a stage on which the object material is placed; a laser module for generating and outputting a laser beam; an optical module for controlling a path of the laser beam; a polygon mirror rotating around an axis of rotation and having a plurality of reflecting surfaces which reflect the laser beam; and a beam guide module for controlling an incidence range within which the laser beam reflected by the polygon mirror is incident on the object material, and an indirect heating method using a laser beam in a heating device.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: October 24, 2023
    Assignee: RNR LAB INC
    Inventor: Jeong Do Ryu
  • Patent number: 11791172
    Abstract: Gas distribution apparatus to provide uniform flows of gases from a single source to multiple processing chambers are described. A valve upstream of a shared volume is controlled by at least two pressurizing sequences during a process it the processing chamber. The first pressurizing sequence opens and closes the upstream valve a first number of cycles and the second pressurizing sequence opens and closes the upstream valve less frequently after the first number of cycles. The open/close timing of the second pressurizing sequence occurs less frequently than the open/close timing of the first pressurizing sequence.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: October 17, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mauro Cimino, Arkaprava Dan, Paul Z. Wirth