Abstract: The present invention relates to a process for irradiating a processed surface (5) of a processed substrate (1) so as to obtain a predefined temperature profile, the processed surface (5) comprising a first area (11) and a second area (13), said first area (11) having a first combination of optical properties and thermal properties, and said second area (13) having a second combination of optical properties and thermal properties, said first combination and second combination being different. A further object of the invention is a system (21) for irradiating a processed surface (5) of a processed substrate (1) so as to obtain a predefined temperature profile, the processed surface (5) comprising a first area (11) and a second area (13), said first area (11) having a first combination of optical properties and thermal properties, and said second area (13) having a second combination of optical properties and thermal properties, said first combination and second combination being different.

Abstract: An interconnect structure includes first, second, and third insulating layers, first, second, and third conductive lines, and first, second, third, and fourth conductive vias. The first conductive line is embedded in the first insulating layer. The second conductive line is embedded in the second insulating layer and comprises a first portion, a second portion, and a third portion. The third conductive line is embedded in the third insulating layer. The first and second conductive via are embedded in the first insulating layer. The third and fourth conductive via are embedded in the second insulating layer. A first cross-sectional area surrounded by the first conductive line, the first conductive via, the second conductive via, the first portion, and the second portion is substantially equal to a second cross-sectional area surrounded by the first portion, the third portion, the third conductive via, the fourth conductive via, and the third conductive line.

Abstract: A substrate processing apparatus includes a processing unit configured to perform a preset processing on a substrate; a transfer unit, including a holder configured to hold the substrate, configured to carry the substrate into/from the processing unit by displacing the holder which holds the substrate; and a substrate inspection unit configured to acquire, at an outside of the processing unit, information indicating a surface state of the substrate held by the holder.

Abstract: A display module and a fabrication method thereof, and a display device, and relates to the field of display technologies, to synchronously implement a display function and a surface tactile reproduction function. The display module includes: a base substrate, a plurality of piezoelectric structures positioned on a first side of the base substrate, and at least one isolation portion positioned on the first side of the base substrate and configured to separate any two adjacent piezoelectric structures. A pixel hole is arranged in at least one of three positions, i.e., a position of the piezoelectric structure, a position of the isolation portion, and a position between the piezoelectric structure and the isolation portion. The display module also includes a plurality of pixel structures, and each of the plurality of pixel structures is positioned in one of the pixel holes.

Abstract: A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.

Abstract: The embodiment provides a graphene-containing membrane producible by wet-coating and excellent in electric properties, a process for producing the membrane, a graphene-containing membrane laminate, and a photoelectric conversion device using the graphene-containing membrane. The graphene-containing membrane contains graphene having a graphene skeleton combined with polyalkylenimine chains. The membrane has a ratio of the photoelectron intensity at the energy peak position of C1s orbital to that at the bonding energy on an X-ray photoelectron spectrum measured on an ITO film of 288 eV in a range of 5.5 to 20. This membrane can be produced by heating a graphene oxide-containing film in the presence of polyalkyleneimine and further heating the film in the presence of a reducing agent. The graphene-containing membrane can be so installed in a photoelectric conversion device that it is placed between the photoelectric conversion layer and the electrode.

Abstract: This application relates to an apparatus and method for processing a wafer. In an embodiment of this application, an apparatus for processing a wafer includes: a heater including a pedestal, where a top portion of the pedestal includes an annular edge step and a wafer pocket recessed relative to the annular edge step to accommodate a wafer; a side ring, including an outer portion and a top portion, where the outer portion surrounds an outer side wall of the pedestal, and the top portion covers an outer portion of the annular edge step and includes a centripetal slant bevel; and a shadow ring, a bottom portion thereof including a slant bevel matching the centripetal slant bevel of the top portion of the side ring.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including checking a leak from a process furnace before a substrate is processed. The checking includes: (a) measuring, by a partial pressure sensor provided at an exhaust pipe, an oxygen partial pressure value of a residual oxygen after the process furnace is vacuum-exhausted; (b) comparing the oxygen partial pressure value measured by the partial pressure sensor with a threshold value; and (c) when the oxygen partial pressure value is higher than the threshold value in (b), performing at least one among: purging the process furnace and evacuating the process furnace.

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.

Abstract: Micro light emitting diode inspection and repairing equipment including a carrying stage, an optical inspection module and an injection device is provided. The optical inspection module is arranged corresponding to the carrying stage to capture image information and obtain a position coordinate from the image information. The injection device is adapted to move to a target position of the carrying stage according to the position coordinate. The injection device includes a tube and a nozzle. The tube includes a first portion and a second portion connected to the first portion. The extending direction of the first portion is different from the extending direction of the second portion. A fluid blows to the target position after passing through the tube and the nozzle. An inspection and repairing method adopting the micro light emitting diode inspection and repairing equipment is also provided.

Abstract: There is provided a technique that includes: performing a set a plurality of times, the set including: (a) loading at least one substrate into a process container; (b) performing a process of forming a nitride film on the at least one substrate by supplying a film-forming gas to the at least one substrate supported by a support in the process container; (c) unloading the processed at least one substrate from an interior of the process container; and (d) supplying an oxidizing gas into the process container from which the processed at least one substrate has been unloaded so as to oxidize one part of the nitride film formed inside the process container in (b) into an oxide film and maintain another part of the nitride film, which is different from the one part of the nitride film, as it is without oxidizing the another part.

Abstract: This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.

Abstract: An image sensor may include a pixel isolation structure disposed in a semiconductor substrate to define a first pixel region, first and second photoelectric conversion regions disposed in the first pixel region, and a separation structure disposed in the first pixel region, between the first and second photoelectric conversion regions. The pixel isolation structure may include first pixel isolation portions, which are spaced apart from each other in a second direction and extend lengthwise in a first direction, and second pixel isolation portions, which are spaced apart from each other in the first direction and extend lengthwise in the second direction to connect to the first pixel isolation portions. The separation structure may be spaced apart from the pixel isolation structure in the first direction and the second direction, and is at least partly at the same level as the first and second photoelectric conversion regions in a third direction perpendicular to the first direction and the second direction.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A temperature of a pedestal comprising a cooling feature on which a substrate is located is set to less than or equal to 100° C. The substrate is exposed to a plasma treatment to remove chemical residual and/or impurities from features of the substrate including a metal bottom, dielectric sidewalls, and/or a field of dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The plasma treatment may be an oxygen plasma, for example, a direct oxygen plasma. Processing tools and computer readable media for practicing the method are also described.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.

Abstract: Provided is a method including at least the thermal treatment step of thermally treating a SOI substrate having a first silicon layer at a first temperature that the diffusion flow rate of an interstitial silicon atom in a silicon single crystal is higher than the diffusion flow rate of an interstitial oxygen atom and the processing step of processing the SOI substrate after the thermal treatment step to obtain a displacement enlarging mechanism.