Patents Examined by Jae Lee
  • Patent number: 10777603
    Abstract: An optical sensor is provided. The optical sensor includes a substrate, a transistor, a first electrode, a photodiode, a second electrode and an anti-reflective layer. The transistor is disposed over the substrate. The first electrode is disposed over the substrate and electrically connected to the transistor. The second electrode is disposed over the first electrode, and the photodiode is disposed between the first electrode and the second electrode. The anti-reflective layer is disposed over the second electrode and a first U-shaped portion lining the second electrode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 15, 2020
    Assignee: INT TECH CO., LTD.
    Inventor: Fu-Yuan Tuan
  • Patent number: 10763297
    Abstract: An optical sensor is provided. The optical sensor includes a substrate, a transistor, a dielectric layer, a first electrode, a photodiode, a second electrode and a gap. The transistor is disposed over the substrate. The dielectric layer is disposed over the transistor. The first electrode is disposed over the dielectric layer and includes a U-shaped portion electrically connected to the transistor. The second electrode is disposed over the first electrode, and the photodiode is disposed between the first electrode and the second electrode. The gap is surrounded by the U-shaped portion of the first electrode and is sealed by the first electrode or the second electrode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 1, 2020
    Assignee: INT TECH CO., LTD.
    Inventor: Fu-Yuan Tuan
  • Patent number: 10756236
    Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Scott D. Schellhammer, Shan Ming Mou, Michael J. Bernhardt
  • Patent number: 10756115
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 25, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Patent number: 10727240
    Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: July 28, 2020
    Assignee: Silicon Store Technology, Inc.
    Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
  • Patent number: 10720381
    Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toyokazu Shibata
  • Patent number: 10707202
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone RascunĂ¡
  • Patent number: 10700208
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Kai-Yu Cheng, Chih-Han Lin, Sin-Yi Yang, Horng-Huei Tseng
  • Patent number: 10700245
    Abstract: A light-emitting device comprising: a base member; a plurality of first light-emitting elements disposed on the base member; a plurality of second light-emitting elements disposed on the base member; a plurality of first wavelength conversion members; and a second wavelength conversion member. The first wavelength conversion members are respectively disposed on or above the first light-emitting elements. The first wavelength conversion members each comprises a light-transmissive body mainly containing an inorganic material, and a first phosphor layer on the lower surface of the light-transmissive body. The second wavelength conversion member is disposed on the base member to cover the second light-emitting elements and the first wavelength conversion members. The second wavelength conversion member comprises an encapsulating resin and second phosphor.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 30, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Yusuke Kawano, Shunsuke Miyajima
  • Patent number: 10692860
    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 23, 2020
    Assignee: HITACHI, LTD.
    Inventors: Ryuusei Fujita, Kumiko Konishi, Akio Shima
  • Patent number: 10685878
    Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Sarah A. Niroumand
  • Patent number: 10686069
    Abstract: A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin Hye Kim, Kyung Seok Oh, Gu Young Cho, Sang Jin Hyun
  • Patent number: 10686075
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Patent number: 10679860
    Abstract: A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 9, 2020
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Lakshmi Kanta Bera, Yee Chong Loke, Surani Bin Dolmanan, Sudhiranjan Tripathy, Wai Hoe Tham
  • Patent number: 10680197
    Abstract: A display device includes a display region, an organic insulating layer, a display element, and a moisture-ingress barrier. The organic insulating layer has a groove outside the display region. The organic insulating layer extends over the display region and a region outside the groove. The display element is disposed in the display region and includes, in order, a first electrode, an organic layer, and a second electrode. The organic layer includes one or more moisture-reacting layers. The moisture-ingress barrier is disposed in the groove of the organic insulating layer, includes a material identical to the material of the one or more moisture-reacting layers, and has a thickness greater than the thickness of the one or more moisture-reacting layers.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 9, 2020
    Assignee: JOLED INC.
    Inventors: Masanori Miura, Atsuhito Murai
  • Patent number: 10672899
    Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
  • Patent number: 10672897
    Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10665610
    Abstract: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hideaki Kuwabara, Saishi Fujikawa
  • Patent number: 10651373
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Patent number: 10651196
    Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 12, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Fei Zhou, Raghuveer S. Makala, Adarsh Rajashekhar