Patents Examined by Jae Lee
  • Patent number: 10411127
    Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Chi, Tenko Yamashita, Chen Zhang
  • Patent number: 10395975
    Abstract: A semiconductor device has a semiconductor substrate where a plurality of elements or penetration electrodes are arranged and a trench is arranged to insulate and separate the plurality of elements or penetrating elements by surrounding the plurality of elements or penetration electrodes. The trench is arranged to penetrate both sides of the semiconductor substrate, and has an inner part where a space is arranged. Accordingly, it is possible to configure a semiconductor device having a structure to suppress insulation breakdown while simplifying a manufacturing process and improving yield of product manufacture.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 27, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yuuki Inagaki, Kazushi Asami, Yasuhiro Kitamura
  • Patent number: 10388759
    Abstract: Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 20, 2019
    Assignees: SHANGHAI TIANMA AM-OLED CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Qiong Xu, Jianjun Zhang
  • Patent number: 10388632
    Abstract: A semiconductor device includes, a plurality of semiconductor dies formed using semiconductor substrates, plane orientations of which are the same, and the plurality of the semiconductor dies are stacked such that a crystal orientation of at least one layer is different from other layers.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Aki Dote
  • Patent number: 10381476
    Abstract: A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on the bottom source/drain layer, forming a recess in the channel layer on a second region of the substrate, wherein the bottom surface of the recess is below the surface of the channel layer on a first region, forming a top source/drain layer on the channel layer, where the top source/drain layer has a greater thickness on the second region of the substrate than on the first region of the substrate, and forming a vertical fin on the first region of the substrate, and a vertical fin on the second region of the substrate, wherein a first top source/drain is formed on the vertical fin on the first region, and a second top source/drain is formed on the vertical fin on the second region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10367024
    Abstract: A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjoo Nah, Jung-Chak Ahn, Kyung-Ho Lee
  • Patent number: 10361303
    Abstract: A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on the bottom source/drain layer, forming a recess in the channel layer on a second region of the substrate, wherein the bottom surface of the recess is below the surface of the channel layer on a first region, forming a top source/drain layer on the channel layer, where the top source/drain layer has a greater thickness on the second region of the substrate than on the first region of the substrate, and forming a vertical fin on the first region of the substrate, and a vertical fin on the second region of the substrate, wherein a first top source/drain is formed on the vertical fin on the first region, and a second top source/drain is formed on the vertical fin on the second region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10361179
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 23, 2019
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • Patent number: 10347825
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Joe Lee, Christopher J. Penny, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10347626
    Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yufei Xiong, Yunlong Liu, Hong Yang, Jianxin Liu
  • Patent number: 10340468
    Abstract: Provided is a display device including a base film and a display-element layer over the base film, the display-element layer having a display region including a plurality of pixels. The base film has a first gap separating the base film into a first region and a second region. The display-element layer possesses an insulating film, and the insulating film extends over the first region and the second region and overlaps with the first gap. The base film may have flexibility.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Japan Display Inc.
    Inventor: Hsiang-Yuan Cheng
  • Patent number: 10325996
    Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
  • Patent number: 10325804
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10325974
    Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a shielding pattern created from a layer identical to a pixel electrode and configured to prevent a display function of a display function layer from being adversely affected by a signal from a signal line.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Like Hu, Xiaoxiang He
  • Patent number: 10312151
    Abstract: Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10312434
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Joe Lee, Christopher J. Penny, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10297728
    Abstract: The present invention provides a molded package for a light emitting device including a molded resin and first and second leads, the exposed surface of the first lead having a first and second edge portions opposed to each other so as to put a mounting area therebetween in a first direction, the first and second edge portions respectively having one first cutout and second cutouts, the mounting area having a size not less than a distance between the first and the second cutouts and less than a distance between the first the second edge portions in the first direction.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 21, 2019
    Assignee: Nichia Corporation
    Inventors: Nobuhide Kasae, Keisuke Sejiki
  • Patent number: 10269855
    Abstract: According to embodiments of the present disclosure, a dynamic photodiode may include a substrate, a first doped region, a second doped region, a first resettable doped region between the first doped region and the second doped region, and a first light absorbing region between the first doped region and the second doped region. The first doped region may include a first contact that receives a first voltage. The second doped region may include a second contact that receives a second voltage. The first resettable doped region may include a first resettable contact that receives a reset voltage or is set as an open circuit. The first light absorbing region may generate first electron-hole pairs in the substrate when the first resettable contact is set as an open circuit, and the first electron-hole pairs may be removed from the substrate when the first resettable contact receives the reset voltage.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 23, 2019
    Assignee: ACTLIGHT SA
    Inventors: Denis Sallin, Maxim Gureev, Alexander Kvasov, Serguei Okhonin
  • Patent number: 10262955
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Patent number: 10256166
    Abstract: A semiconductor device includes a resin case which houses a semiconductor element, a plurality of lead frames disposed in the principal plane of a base of the resin case with spaces therebetween, and a block portion disposed over a space between adjacent lead frames along the adjacent lead frames. With the semiconductor device, the disposition of the block portion makes creepage distance long, compared with a case where the block portion is not disposed and therefore a space between the adjacent lead frames is flat. Accordingly, even if metal atoms contained in the lead frames or the like migrate on an insulator or at an interface because of migration, a conduction path is hardly formed between the adjacent lead frames. That is to say, a short circuit hardly occurs between the adjacent lead frames with the block portion therebetween. This semiconductor device provides improved reliability.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masanori Tanaka, Tadanori Yamada