Patents Examined by Jae Lee
  • Patent number: 11145630
    Abstract: A light emitting diode panel including a first substrate, a second substrate and a plurality of display units is provided. The display units are disposed between the first substrate and the second substrate. One display unit has multiple first regions and a second region surrounded by the first regions and includes multiple first light emitting diodes, multiple control signal lines and a second light emitting diode. Every N first light emitting diodes construct one pixel unit located within one of the first regions, wherein N is an integer greater than 1. The control signal lines are disposed on the first substrate and each extends toward one first light emitting diode. The second light emitting diode is disposed on the first substrate, located within the second region, and surrounded by the first regions. The second light emitting diode is electrically connected to one of the control signal lines.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Lung Lo, Pin-Miao Liu, Jhao-Wun Chen, Tsung-Tien Wu
  • Patent number: 11139226
    Abstract: A semiconductor package structure includes a vapor chamber, a plurality of electrical contacts, a semiconductor die and an encapsulant. The vapor chamber defines an enclosed chamber for accommodating a working liquid. The electrical contacts surround the vapor chamber. The semiconductor die is disposed on the vapor chamber, and electrically connected to the electrical contacts through a plurality of bonding wires. The encapsulant covers a portion of the vapor chamber, portions of the electrical contacts, the semiconductor die and the bonding wires.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin-En Chen, Ian Hu, Hung-Hsien Huang
  • Patent number: 11139333
    Abstract: A photodetector sensor array device as usable for camera chips comprises upper and lower contact layers of n+ and p+ semiconductor material either side of a light absorbing region made of either one layer, or two oppositely doped layers, of semiconductor material. Insulating trenches of dielectric material extending through the layers to form the individual pixels. Respective contacts are connected to the upper and lower contact layers so that each pixel can be reverse biased or forward biased. In operation, the device is reset with a reverse bias, and then switched to forward bias for sensing. After switching, carriers generated in response to photon absorption accumulate in potential wells in the light absorbing region and so reduce the potential barriers to the contact layers, which causes current to start to flow between the contacts after a time delay which is inversely proportional to the incident light intensity.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 5, 2021
    Assignee: ACTLIGHT SA
    Inventors: Serguei Okhonin, Maxim Gureev, Denis Sallin
  • Patent number: 11133179
    Abstract: A thin-film structure includes a support layer and a dielectric layer on the support layer. The support layer includes a material having a lattice constant. The dielectric layer includes a compound having a Ruddlesden-Popper phase (An+1BnX3n+1). where A and B each independently include a cation, X is an anion, and n is a natural number. The lattice constant of the material of the support layer may be less than a lattice constant of the compound.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 28, 2021
    Assignees: Samsung Electronics Co., Ltd., Cornell University
    Inventors: Kiyoung Lee, Woojin Lee, Myoungho Jeong, Yongsung Kim, Eunsun Kim, Hyosik Mun, Jooho Lee, Changseung Lee, Kyuho Cho, Darrell G. Schlom, Craig J. Fennie, Natalie M. Dawley, Gerhard H. Olsen, Zhe Wang
  • Patent number: 11133205
    Abstract: Apparatus and methods to process one or more substrate are described. A processing chamber comprises a support assembly, a chamber lid, and a controller. The chamber lid has a front surface facing the support assembly, a first sensor on the front surface and a second sensor on the front surface, the first sensor positioned at a first distance from the central rotational axis, and the second sensor positioned at a second distance from the central rotational axis greater than the first distance. The controller is configured to determine if a substrate is within or outside of the substrate support region of the support assembly.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sanggyum Kim, Prasanth Narayanan, Subramanian Tamilmani, Mandyam Sriram
  • Patent number: 11121120
    Abstract: An interposer includes a polycrystalline ceramic core disposed between a first surface and a second surface of the interposer, an adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the adhesion layer, and one or more electrically conductive vias extending from the first surface to the second surface through the polycrystalline ceramic core, the adhesion layer, and the barrier layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 14, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 11114480
    Abstract: A photodetector device comprising n-type and p-type light absorbing regions arranged to form a pn-junction and n+ and p+ contact regions connected to respective contacts. The light absorbing regions and the contact regions are arranged in a sequence n+ p n p+ so that, after a voltage applied between the n+ and p+ contacts is switched from a reverse bias to a forward bias, electrons and holes which are generated in the light absorbing regions in response to photon absorption drift towards the p+ and n+ contact regions respectively, which causes current to start to flow between the contacts after a time delay which is inversely proportional to the incident light intensity.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 7, 2021
    Assignee: ACTLIGHT SA
    Inventors: Serguei Okhonin, Maxim Gureev, Denis Sallin
  • Patent number: 11114319
    Abstract: A heat treatment apparatus includes a heating unit provided around a processing container accommodating a substrate; a plurality of blowing units configured to blow a cooling medium into a space between the processing container and the heating unit; and a shutter configured to simultaneously opens/closes at least two of the plurality of blowing units and including a slit formed corresponding to each of the blowing units.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 7, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Yasuaki Kikuchi, Koji Yoshii, Wataru Nakajima, Norio Baba
  • Patent number: 11114555
    Abstract: A high electron mobility transistor device includes a substrate, a plurality of pairs of alternating layers, at least one stress-relief layer and a gallium nitride layer. The plurality of pairs of alternating layers is disposed over the substrate, and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer. The stress-relief layer is disposed between the pairs of alternating layers. The gallium nitride layer is disposed over the alternating layers.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 7, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chi-Feng Hsieh, Tuan-Wei Wang, Chien-Jen Sun
  • Patent number: 11107678
    Abstract: An apparatus is provided. The apparatus has a chuck having a first side configured to retain a superstrate or a template and a second side, an array of image sensors disposed at the second side of the chuck and spaced from the chuck, and an array of light sources disposed between the transparent chuck and the array of image sensors.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 31, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Byung-Jin Choi
  • Patent number: 11098402
    Abstract: A novel method, composition and storage and delivery container for using antimony-containing dopant materials are provided. The composition is selected with sufficient vapor pressure to flow at a steady, sufficient and sustained flow rate into an arc chamber as part of an ion implant process. The antimony-containing material is represented by a non-carbon containing chemical formula, thereby reducing or eliminating the introduction of carbon-based deposits into the ion chamber. The composition is stored in a storage and delivery vessel under stable conditions, which includes a moisture-free environment that does not contain trace amounts of moisture. The storage and delivery container is specifically designed to allow delivery of high purity, vapor phase antimony-containing dopant material at a steady, sufficient and sustained flow rate.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 24, 2021
    Assignee: Praxair Technology, Inc.
    Inventors: Aaron Reinicker, Ashwini K Sinha, Douglas C. Heiderman
  • Patent number: 11088094
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Patent number: 11081560
    Abstract: A semiconductor device and methods for forming the same are provided. The method includes providing a substrate having a first conductive type, forming an epitaxial layer having the first conductive type on the substrate, forming a trench in the epitaxial layer, forming a first insulating layer in the trench and on the top surface of the epitaxial layer, forming a shield electrode and a mask layer on the first insulating layer in order, using the mask layer to remove a portion of the first insulating layer, wherein the top surface of the first insulating layer is higher than the top surface of the shield electrode after removing the portion of the first insulating layer, removing the mask layer, forming a second insulating layer on the first insulating layer and the shield electrode, and forming a gate electrode on the second insulating layer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 3, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Yeh Chen, Sheng-Wei Fu, Chung-Yeh Lee
  • Patent number: 11075084
    Abstract: Methods for fabricating a 3D NAND flash memory are disclosed. The method includes the steps of forming a hardmask pattern on the hardmask layer, and using the hardmask pattern to form apertures in the alternating layers by selectively plasma etching the alternating layers versus the hardmask layer using a hydrofluorocarbon etching gas selected from the group consisting of 1,1,1,3,3,3-hexafluoropropane (C3H2F6), 1,1,2,2,3,3-hexafluoropropane (iso-C3H2F6), 1,1,1,2,3,3,3-heptafluoropropane (C3HF7), and 1,1,1,2,2,3,3-heptafluoropropane (iso-C3HF7), wherein the first etching layer comprises a material different from that of the second etching layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 27, 2021
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Peng Shen, Keiichiro Urabe, Jiro Yokota, Nicolas Gosset
  • Patent number: 11056536
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11049776
    Abstract: A semiconductor memory device includes a first chip having a first pad and a first misalignment detection pattern on a first surface; and a second chip having a second pad and a second misalignment detection pattern on a second surface, and bonded to the first surface of the first chip such that the second pad is coupled with the first pad. The second chip includes a misalignment detection circuit which is coupled between the second misalignment detection pattern and a test pad and outputs a first voltage provided from the first misalignment detection pattern, to the test pad, in the case where a misalignment between the first chip and the second chip exceeds a preset value such that the first misalignment detection pattern and the second misalignment detection pattern are shorted to each other.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Jung
  • Patent number: 11037866
    Abstract: A semiconductor device has inner leads (2a) of leads (2) which are covered with a first resin-encapsulating body (4), and has outer leads (2b) which are exposed from the first resin-encapsulating body (4), and which are given a shape bending downward and have distal ends having the bending shape extending in a lateral direction. The inner leads (2a) embedded in the first resin-encapsulating body (4) extend inward, and are then formed into a shape bending downward. Above end portions (3) having the bending shape, an element mounting portion (11) is formed of the first resin-encapsulating body (4), and a semiconductor element (6) placed on the element mounting portion (11) is covered with a second resin-encapsulating body (8).
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 15, 2021
    Assignee: ABLIC INC.
    Inventor: Yasuhiro Taguchi
  • Patent number: 11024554
    Abstract: A wiring substrate includes an insulating substrate being square in plan view, the insulating substrate including one main surface with a recess, and the other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate. The external electrodes are arranged in a row in a peripheral section of the insulating substrate. In plan view, an area of one of the external electrodes located at a center of each side of the insulating substrate is larger than an area of one of the external electrodes located at an edge of the each side.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 1, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Hiroshi Kawagoe
  • Patent number: 11024718
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 11018221
    Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Chun Yu Wong, Haiting Wang, Yong Jun Shi, Xiaoming Yang, Liu Jiang